The eZ8 CPU is an extension of the Z8 CPU architecture. The eZ8 executes all Z8 instructions except the WDH (Watch Dog Timer Enable During Halt Mode). The eZ8 features new instructions and access to a larger register file.
EZ8 REGISTER SET
The following is a list of the eZ8 registers used by ASEZ8:
r0 ... r15 - 8-bit accumulators
rr0 ... rr15 - 16-bit accumulators
EZ8 INSTRUCTION SET
The following list specifies the format for each addressing
mode supported by ASEZ8:
#data immediate byte data
addr location/branch address
r0 ... r15 8-bit registers
rr0 ... rr15 16-bit registers
@rn or register indirect addressing
(rn)
@rrn or register indirect addressing
(rrn)
@.RR(addr) register pair indirect
where addr is truncated to
4-bits and made even
@addr or indirect addressing
(addr)
offset(rn) indexed register addressing
CC condition codes
The terms data, addr, and offset may all be expressions.
The designation CC refers to a condition code argument. The
following table contains all the valid condition codes supported
by ASEZ8:
f Always False -
t Always True -
c Carry C=1
nc No Carry C=0
z Zero Z=1
nz Non-Zero Z=0
pl Plus S=0
mi Minus S=1
ov Overflow V=1
nov No Overflow V=0
eq Equal Z=1
ne Not Equal Z=0
ge Greater Than or Equal (S XOR V)=0
lt Less Than (S XOR V)=1
gt Greater Than (Z OR (S XOR V))=0
le Less Than or Equal (Z OR (S XOR V))=1
uge Unsigned ge C=0
ult Unsigned lt C=1
ugt Unsigned gt (C=0 AND Z=0)=1
ule Unsigned le (C OR Z)=1
The following tables list all eZ8 mnemonics recognized by the
ASEZ8 assembler. The designation [] refers to a required ad-
dressing mode argument. (The new instructions of the eZ8 are
denoted by a *) Note that not all addressing modes are valid
with every instruction, refer to the eZ8 technical data for
valid modes.
Arithmetic Instructions
adc [],[] add [],[]
adcx* [],[] addx* [],[]
cp [],[] cpc* [],[]
cpx* [],[] cpcx* [],[]
da [] mult* []
dec [] decw []
inc [] incw []
sbc [],[] sbcx* [],[]
sub [],[] subx* [],[]
Bit Manipulation Instructions
bclr* [],[] bset* [],[]
bit* [],[],[] bswap* []
ccf
rcf scf
tcm [],[] tcmx* [],[]
tm [],[] tcx* [],[]
Block Transfer Instructions
ldci* [],[] ldei [],[]
CPU Control Instructions
atm* ccf
di ei
halt nop
rcp scf
srp [] stop
wdt
Load Instructions
clr [] ld [],[]
ldc* [],[] ldci* [],[]
lde [],[] ldei [],[]
ldx* [],[] ldwx* [],[]
lea* [],[]
pop [] popx* []
push [] pushx* []
Logical Instructions
and [],[] andx* [],[]
com []
or [],[] orx* [],[]
xor [],[] xorx* [],[]
Program Control Instructions
brk* btj* [],[],[],[]
btjnz* [],[],[] btjz* [],[],[]
call [] djnz [],[]
iret
jp [] jp CC,[]
jr [] jr CC,[]
ret trap* []
Rotate and Shift Instructions
bswap* []
rl [] rlc []
rr [] rrc []
sra [] srl* []
swap []
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Last Updated: September 2023