APPENDIX D ASRS08 ASSEMBLER D-1 D.1 RS08 MICROPROCESSORS D-1 D.2 RS08 REGISTER SET D-2 D.3 RS08 ARGUMENT SYNTAX D-2 D.4 RS08 INSTRUCTIONS D-3 APPENDIX D ASRS08 ASSEMBLER D.1 RS08 MICROPROCESSORS The ASRS08 assembler supports the RS08 series of microproces- sors. Processor specific definition files are included for the KA2(KA1), KA8(KA4), KB8( KB2, KB4, and KB6), LA8, and LE4 varia- tions of peripheral options with the RS08 core. ASRS08 ASSEMBLER PAGE D-2 RS08 MICROPROCESSORS D.2 RS08 REGISTER SET The following is a list of the RS08 registers used by ASRS08: a - the accumulator x - the index register D.3 RS08 ARGUMENT SYNTAX a 8 bit accumulator register x 8 bit index register #opr8i 8 bit immediate value (#)n 3 bit data M is a memory address opr16a 16 bit address opr8a 8 bit address opr5a 5 bit address (0 <= opra5 <= 31) opra4 4 bit address (0 <= opra4 <= 15) Force the opr8a address form using the * prefix Force the opr5a or opr4a form using the <* prefix rel -128 to +127 relative address ,x indexed addressing D[X] indexed addressing The terms opr8i, n, opr16a, opr8a, opra5, opra4, and rel may be expressions. Note that not all addressing modes are valid with every in- struction. Refer to the RS08 reference manual for more details. ASRS08 ASSEMBLER PAGE D-3 RS08 ARGUMENT SYNTAX D.4 RS08 INSTRUCTIONS The following tables list the mnemonics and arguments recog- nized by the ASRS08 assembler. The operational description of the instructions may contain one or more of the following forms: A is a register X is a register C is the Carry Bit n is a 3 Bit Value # is an immediate value (arg) - 'The Contents Of' arg (Mx) - 'The Contents Of M Addressed By (x)' Load and Store Instructions lda #opr8i A <- # lda opr8a A <- (M) lda opra5 A <- (M) lda ,x A <- (Mx) lda D[X] A <- (Mx) ldx #opr8i X <- # ldx opr8a X <- (M) ldx ,x X <- (Mx) ldx D[X] X <- (Mx) sta opr8a (M) <- (A) sta opr5a (M) <- (A) sta ,x (Mx) <- (A) sta D[X] (Mx) <- (A) stx opr8a (M) <- (X) tax X <- (A) txa A <- (X) ASRS08 ASSEMBLER PAGE D-4 RS08 INSTRUCTIONS BSET, BCLR, and Move Instructions bclr n,opr8a Bit n of (M) <- 0 bclr n,x Bit n of (Mx) <- 0 bclr n,D[X] Bit n of (Mx) <- 0 bset n,opr8a Bit n of (M) <- 1 bset n,x Bit n of (Mx) <- 1 bset n,D[X] Bit n of (Mx) <- 1 mov opr8a,opr8a (M)dst <- (M)src mov #opr8i,opr8a (M) <- # mov ,x,opr8a (M) <- (Mx) mov D[X],opr8a (M) <- (Mx) mov opr8a,D[X] (Mx) <- (M) mov #opr8i,D[X] (Mx) <- # Add and Subtract Instructions adc #opr8i A <- (A) + (C) + # adc opr8a A <- (A) + (C) + (M) adc ,x A <- (A) + (C) + (Mx) adc D[X] A <- (A) + (C) + (Mx) adc x A <- (A) + (C) + (x) adcx A <- (A) + (C) + (x) add #opr8i A <- (A) + # add opr8a A <- (A) + (M) add opr4a A <- (A) + (M) add ,x A <- (A) + (Mx) add D[X] A <- (A) + (Mx) add x A <- (A) + (x) addx A <- (A) + (x) sbc #opr8i A <- (A) - (C) - # sbc opr8a A <- (A) - (C) - (M) sbc ,x A <- (A) - (C) - (Mx) sbc D[X] A <- (A) - (C) - (Mx) sbc x A <- (A) - (C) - (x) sbcx A <- (A) - (C) - (x) sub #opr8i A <- (A) - # sub opr8a A <- (A) - (M) sub opr4a A <- (A) - (M) sub ,x A <- (A) - (Mx) sub D[X] A <- (A) - (Mx) sub x A <- (A) - (x) subx A <- (A) - (x) ASRS08 ASSEMBLER PAGE D-5 RS08 INSTRUCTIONS Other Arithmetic Instructions inc opr8a (M) <- (M) + 1 inc opr4a (M) <- (M) + 1 inc ,x (Mx) <- (Mx) + 1 inc D[X] (Mx) <- (Mx) + 1 inc a A <- (A) + 1 inc x X <- (X) + 1 inca A <- (A) + 1 incx X <- (X) + 1 dec opr8a (M) <- (M) - 1 dec opr4a (M) <- (M) - 1 dec ,x (Mx) <- (Mx) - 1 dec D[X] (Mx) <- (Mx) - 1 dec a A <- (A) - 1 dec x X <- (X) - 1 deca A <- (A) - 1 decx X <- (X) - 1 clr opr8a (M) <- 0 clr opr4a (M) <- 0 clr ,x (Mx) <- 0 clr D[X] (Mx) <- 0 clr a A <- 0 clr x X <- 0 clra A <- 0 clrx X <- 0 cmp #opr8i (A) - # cmp opr8a (A) - (M) cmp ,x (A) - (Mx) cmp D[X] (A) - (Mx) cmp x (A) - (X) cmpx (A) - (X) tst opr8a (M) - 0 tst ,x (Mx) - 0 tst D[X] (Mx) - 0 tst a (A) - 0 tst x (X) - 0 tsta (A) - 0 tstx (X) - 0 ASRS08 ASSEMBLER PAGE D-6 RS08 INSTRUCTIONS Logical Operation Instructions and #opr8i A <- (A) & # and opr8a A <- (A) & (M) and ,x A <- (A) & (Mx) and D[X] A <- (A) & (Mx) and x A <- (A) & (X) andx A <- (A) & (X) ora #opr8i A <- (A) | # ora opr8a A <- (A) | (M) ora ,x A <- (A) | (Mx) ora D[X] A <- (A) | (Mx) ora x A <- (A) | (X) orax A <- (A) | (X) eor #opr8i A <- (A) ^ # eor opr8a A <- (A) ^ (M) eor ,x A <- (A) ^ (Mx) eor D[X] A <- (A) ^ (Mx) eor x A <- (A) ^ (X) eorx A <- (A) ^ (X) com a A <- ~(A) coma A <- ~(A) Shift and Rotate Instructions asl a C <- (A7) Left Shift (A0) <- 0 asla C <- (A7) Left Shift (A0) <- 0 lsl a C <- (A7) Left Shift (A0) <- 0 lsla C <- (A7) Left Shift (A0) <- 0 lsr a 0 -> (A7) Right Shift (A0) -> C lsra 0 -> (A7) Right Shift (A0) -> C rol a C <- (A7) Left Rotate (A0) <- C rola C <- (A7) Left Rotate (A0) <- C ror a C -> (A7) Right Rotate (A0) -> C rora C -> (A7) Right Rotate (A0) -> C ASRS08 ASSEMBLER PAGE D-7 RS08 INSTRUCTIONS Jump and Branch Instructions jmp opr16a PC <- Adrress bcc rel Branch if Carry Bit Clear bcs rel Branch if Carry Bit Set (blo) beq rel Branch if Zero Bit Set bhs rel Branch if Higher or Same (bcc) blo rel Branch if Lower (bcs) bne rel Branh if Zero Bit Clear bra rel Branch Always brn rel Branch Never Bit Branches and Loop Control Instructions brclr n,opr8a,rel Branch if Bit n of (M) is Clear brclr n,D[X],rel Branch if Bit n of (Mx) is Clear brclr n,x,rel Branch if Bit n of (x) is Clear brset n,opr8a,rel Branch if Bit n of (M) is Set brset n,D[X],rel Branch if Bit n of (Mx) is Set brset n,x,rel Branch if Bit n of (x) is Set cbeqa #opr8i,rel Branch if (A) = # cbeq a,#opr8i,rel Branch if (A) = # cbeq opr8a,rel Branch if (M) = 0 cbeq ,x,rel Branch if (Mx) = 0 cbeq D[X],rel Branch if (Mx) = 0 cbeqx rel Branch if (X) = 0 cbeq x,rel Branch if (X) = 0 dbnz opr8a,rel (M) <- (M) - 1, Branch if (M) != 0 dbnz ,x,rel (Mx) <- (Mx) - 1, Branch if (Mx) != 0 dbnz D[X],rel (Mx) <- (Mx) - 1, Branch if (Mx) != 0 dbnz a,rel A <- (A) - 1, Branch if (A) != 0 dbnza rel A <- (A) - 1, Branch if (A) != 0 dbnz x,rel X <- (X) - 1, Branch if (X) != 0 dbnzx rel X <- (X) - 1, Branch if (X) != 0 ASRS08 ASSEMBLER PAGE D-8 RS08 INSTRUCTIONS Subroutine Related Instructions bsr rel Branch to Subroutine jsr opr16a Jump to Subroutine rts Return from Subroutine sha (A) <--> Shadow PC High sla (A) <--> Shadow PC Low Miscellaneous Instructions nop No Operation sec (C) <- 1 clc (C) <- 0 bgnd Background wait Put MCU into wait mode stop Put MCU into stop mode