) will be
generated in the assembly listing if the first 79 characters in
two or more labels are the same. The code is generated because the symbols location is
changing on each pass through the source file.
The label must not start with the characters 0-9, as this
designates a reusable symbol with special attributes described
in a later section.
The label must not start with the sequence $$, as this
represents the temporary radix 16 for constants.
THE ASSEMBLER PAGE 1-6
SOURCE PROGRAM FORMAT
1.2.1.2 Operator Field -
The operator field specifies the action to be performed. It
may consist of an instruction mnemonic (op code) or an assembler
directive.
When the operator is an instruction mnemonic, a machine in-
struction is generated and the assembler evaluates the addresses
of the operands which follow. When the operator is a directive
ASxxxx performs certain control actions or processing operations
during assembly of the source program.
Leading and trailing spaces or tabs in the operator field
have no significance; such characters serve only to separate
the operator field from the preceeding and following fields.
An operator is terminated by a space, tab or end of line.
1.2.1.3 Operand Field -
When the operator is an instruction mnemonic (op code), the
operand field contains program variables that are to be
evaluated/manipulated by the operator.
Operands may be expressions or symbols, depending on the
operator. Multiple expressions used in the operand fields may
be separated by a comma. An operand should be preceeded by an
operator field; if it is not, the statement will give an error
( errors.
THE ASSEMBLER PAGE 1-13
SYMBOLS AND EXPRESSIONS
Example of reusable symbols:
a: ldx #atable ;get table address
lda #0d48 ;table length
1$: clr ,x+ ;clear
deca
bne 1$
b: ldx #btable ;get table address
lda #0d48 ;table length
1$: clr ,x+ ;clear
deca
bne 1$
1.3.4 Current Location Counter
The period (.) is the symbol for the current location coun-
ter. When used in the operand field of an instruction, the
period represents the address of the first byte of the
instruction:
AS: ldx #. ;The period (.) refers to
;the address of the ldx
;instruction.
When used in the operand field of an ASxxxx directive, it
represents the address of the current byte or word:
QK = 0
.word 0xFFFE,.+4,QK ;The operand .+4 in the .word
;directive represents a value
;stored in the second of the
;three words during assembly.
If we assume the current value of the program counter is
0H0200, then during assembly, ASxxxx reserves three words of
storage starting at location 0H0200. The first value, a hex-
adecimal constant FFFE, will be stored at location 0H0200. The
second value represented by .+4 will be stored at location
0H0202, its value will be 0H0206 ( = 0H0202 + 4). The third
value defined by the symbol QK will be placed at location
0H0204.
At the beginning of each assembly pass, ASxxxx resets the lo-
cation counter. Normally, consecutive memory locations are
assigned to each byte of object code generated. However, the
THE ASSEMBLER PAGE 1-14
SYMBOLS AND EXPRESSIONS
value of the location counter can be changed through a direct
assignment statement of the following form:
. = . + expression
The new location counter can only be specified relative to
the current location counter. Neglecting to specify the current
program counter along with the expression on the right side of
the assignment operator will generate the <.> error. (Absolute
program areas may use the .org directive to specify the absolute
location of the current program counter.)
The following coding illustrates the use of the current location
counter:
.area CODE1 (ABS) ;program area CODE1
;is ABSOLUTE
.org 0H100 ;set location to
;0H100 absolute
num1: ldx #.+0H10 ;The label num1 has
;the value 0H100.
;X is loaded with
;0H100 + 0H10
.org 0H130 ;location counter
;set to 0H130
num2: ldy #. ;The label num2 has
;the value 0H130.
;Y is loaded with
;value 0H130.
.area CODE2 (REL) ;program area CODE2
;is RELOCATABLE
. = . + 0H20 ;Set location counter
;to relocatable 0H20 of
;the program section.
num3: .word 0 ;The label num3 has
;the value
;of relocatable 0H20.
. = . + 0H40 ;will reserve 0H40
;bytes of storage as will
THE ASSEMBLER PAGE 1-15
SYMBOLS AND EXPRESSIONS
.blkb 0H40 ;or
.blkw 0H20
The .blkb and .blkw directives are the preferred methods of
allocating space.
1.3.5 Numbers
ASxxxx assumes that all numbers in the source program are to
be interpreted in decimal radix unless otherwise specified. The
.radix directive may be used to specify the default as octal,
decimal, or hexadecimal. Individual numbers can be designated
as binary, octal, decimal, or hexadecimal through the temporary
radix prefixes shown in table 6.
Negative numbers must be preceeded by a minus sign; ASxxxx
translates such numbers into two's complement form. Positive
numbers may (but need not) be preceeded by a plus sign.
Numbers are always considered to be absolute values, therefor
they are never relocatable.
1.3.6 Terms
A term is a component of an expression and may be one of the
following:
1. A number.
2. A symbol:
1. A period (.) specified in an expression causes the
current location counter to be used.
2. A User-defined symbol.
3. An undefined symbol is assigned a value of zero and
inserted in the User-Defined symbol table as an un-
defined symbol.
3. A single quote followed by a single ascii character, or
a double quote followed by two ascii characters.
4. An expression enclosed in parenthesis. Any expression
so enclosed is evaluated and reduced to a single term
before the remainder of the expression in which it
appears is evaluated. Parenthesis, for example, may be
THE ASSEMBLER PAGE 1-16
SYMBOLS AND EXPRESSIONS
used to alter the left-to-right evaluation of expres-
sions, (as in A*B+C versus A*(B+C)), or to apply a un-
ary operator to an entire expression (as in -(A+B)).
5. A unary operator followed by a symbol or number.
1.3.7 Expressions
Expressions are combinations of terms joined together by
binary operators. Expressions reduce to a value. The evalua-
tion of an expression includes the determination of its attri-
butes. A resultant expression value may be one of three types
(as described later in this section): relocatable, absolute,
and external.
Expressions are evaluate with an operand hierarchy as follows:
* / % multiplication,
division, and
modulus first.
+ - addition and
subtraction second.
<< >> left shift and
right shift third.
^ exclusive or fourth.
& logical and fifth.
| logical or last
except that unary operators take precedence over binary
operators.
A missing or illegal operator terminates the expression
analysis, causing error codes Phase error: label location changing between passes
THE ASSEMBLER PAGE 1-63
ERRORS
2 and 3. Normally caused by having more than one
level of forward referencing.
er-
rors.
The .endm directive may be followed by a comment field, as
shown below:
.endm ;end of macro
A comment may follow the dummy argument list in a .macro
directive, as shown below:
.macro typemsg message ;Type a message.
jsr typemsg
.word message
.endm ;End of typemsg
The final statement of every macro definition must be a .endm
directive. The .endm directive is also used to terminate inde-
finite repeat blocks and repeat blocks. A .endm directive en-
countered outside a macro definition is flagged with an in the assembly
listing.
2.3.6 Concatenation of Macro Arguments
The apostrophe or single quote character (') operates as a
legal delimiting character in macro definitions. A single quote
that precedes and/or follows a dummy argument in a macro defini-
tion is removed, and the substitution of the real argument oc-
curs at that point. For example, in the following statements:
THE MACRO PROCESSOR PAGE 2-11
ARGUMENTS IN MACRO DEFINITIONS AND MACRO CALLS
.macro def A,B,C
A'B: asciz "C"
.byte ''A,''B
.endm
when the macro def is called through the statement:
def x,y,^/V05.00/
it is expanded, as follows:
xy: asciz "V05.00"
.byte 'x,'y
In expanding the first line, the scan for the first argument
terminates upon finding the first apostrophe (') character.
Since A is a dummy argument, the apostrphe (') is removed. The
scan then resumes with B; B is also noted as another dummy ar-
gument. The two real arguments x and y are then concated to
form the label xy:. The third dummy argument is noted in the
operand field of the .asciz directive, causing the real argument
V05.00 to be substituted in this field.
When evaluating the arguments of the .byte directive during
expansion of the second line, the scan begins with the first
apostrophe (') character. Since it is neither preceded nor fol-
lowed by a dummy argument, this apostrophe remains in the macro
expansion. The scan then encounters the second apostrophe,
which is followed by a dummy argument and is therefor discarded.
The scan of argument A is terminated upon encountering the comma
(,). The third apostrophe is neither preceded nor followed by a
dummy argument and again remains in the macro expansion. The
fourth (and last) apostrophe is followed by another dummy argu-
ment and is likewise discarded. (Four apostrophe (') characters
were necessary in the macro definition to generate two apos-
trophe (') characters in the macro expansion.)
THE MACRO PROCESSOR PAGE 2-12
MACRO ATTRIBUTE DIRECTIVES
2.4 MACRO ATTRIBUTE DIRECTIVES
The ASxxxx assemblers have four directives that allow the
user to determine certain attributes of macro arguments: .narg,
.nchr, .ntyp, and .nval. The use of these directives permits
selective modifications of a macro expansion, depending on the
nature of the arguments being passed. These directives are
described below.
2.4.1 .narg Directive
Format:
[label:] .narg symbol
where: label represents an optional statement label.
symbol represents any legal symbol. This symbol
is equated to the number of arguments in
the macro call currently being expanded.
If a symbol is not specified, the .narg
directive is flagged with a or
to be generated
depending upon the context of the expression itself.
At assembly time the value of an external (global) expression
is equal to the value of the absolute part of that expression.
For example, the expression external+4, where 'external' is an
external symbol, has the value of 4. This expression, however,
THE ASSEMBLER PAGE 1-17
SYMBOLS AND EXPRESSIONS
when evaluated at link time takes on the resolved value of the
symbol 'external', plus 4.
Expressions, when evaluated by ASxxxx, are one of three
types: relocatable, absolute, or external. The following dis-
tinctions are important:
1. An expression is relocatable if its value is fixed re-
lative to the base address of the program area in which
it appears; it will have an offset value added at link
time. Terms that contain labels defined in relocatable
program areas will have a relocatable value; simi-
larly, a period (.) in a relocatable program area,
representing the value of the current program location
counter, will also have a relocatable value.
2. An expression is absolute if its value is fixed. An
expression whose terms are numbers and ascii characters
will reduce to an absolute value. A relocatable ex-
pression or term minus a relocatable term, where both
elements being evaluated belong to the same program
area, is an absolute expression. This is because every
term in a program area has the same relocation bias.
When one term is subtracted from the other the reloca-
tion bias is zero.
3. An expression is external (or global) if it contains a
single global reference (plus or minus an absolute ex-
pression value) that is not defined within the current
program. Thus, an external expression is only par-
tially defined following assembly and must be resolved
at link time.
1.4 GENERAL ASSEMBLER DIRECTIVES
An ASxxxx directive is placed in the operator field of the
source line. Only one directive is allowed per source line.
Each directive may have a blank operand field or one or more
operands. Legal operands differ with each directive.
THE ASSEMBLER PAGE 1-18
GENERAL ASSEMBLER DIRECTIVES
1.4.1 .module Directive
Format:
.module name
The .module directive causes the name to be included in the
assemblers output file as an identifier for this particular ob-
ject module. The name may be from 1 to 79 characters in length.
The name may not have any embedded white space (spaces or tabs).
Only one identifier is allowed per assembled module. The main
use of this directive is to allow the linker to report a
modules' use of undefined symbols. At link time all undefined
symbols are reported and the modules referencing them are
listed.
1.4.2 .title Directive
Format:
.title string
The .title directive provides a character string to be placed
on the second line of each page during listing. The string be-
gins with the first non white space character (after any space
or tab) and ends with the end of the line.
1.4.3 .sbttl Directive
Format:
.sbttl string
The .sbttl directive provides a character string to be placed
on the third line of each page during listing. The string be-
gins with the first non white space character (after any space
or tab) and ends with the end of the line.
THE ASSEMBLER PAGE 1-19
GENERAL ASSEMBLER DIRECTIVES
1.4.4 .list and .nlist Directives
Format:
.list ;Basic .list
.list expr ;with expression
.list (arg1,arg2,...,argn) ;with sublist options
.nlist ;Basic .nlist
.nlist expr ;with expression
.nlist (arg1,arg2,...,argn) ;with sublist options
The .list and .nlist directives control the listing output to
the .lst file. The directives have the following sublist
options:
err - errors
loc - program location
bin - binary output
eqt - symbol or .if evaluation
cyc - opcode cycle count
lin - source line number
src - source line text
pag - pagination
lst - .list/.nlist line listing
md - macro definition listing
me - macro expansion listing
meb - macro expansion binary listing
! - sets the listing mode to
!(.list) or !(.nlist) before
applying the sublist options
The 'normal' listing mode .list is the combination of err, loc,
bin, eqt, cyc, lin, src, pag, lst, and md enabled with me and
meb disabled. The 'normal' listing mode .nlist has all sublist
items disabled. When specifying sublist options the option list
must be enclosed within parenthesis and multiple options
separated by commas.
The NOT option, !, is used to set the listing mode to the op-
posite of the .list or .nlist directive before applying the
sublist options. For example:
THE ASSEMBLER PAGE 1-20
GENERAL ASSEMBLER DIRECTIVES
.nlist (!) is equivalent to .list and
.list (!) is equivalent to .nlist
any additional options will
be applied normally
Normal .list/.nlist processing is disabled within false con-
ditional blocks. However, the .list/.nlist with an expression
can override this behavior if the expression has a non zero
value.
Examples of listing options:
.list (meb) ; macro processing lists only
; generated binary and location
.list (me) ; listing options are enabled
; during macro processing
.nlist (src) ; .nlist src lines not listed
.nlist (!,lst) ; list all except .nlist
.nlist ; combination lists only
.list (src) ; the source line
.list (!,src) ; list only the source line
.list 1 ; enable listing even within
; a FALSE conditional block
1.4.5 .page Directive
Format:
.page
The .page directive causes a page ejection with a new heading
to be printed. The new page occurs after the next line of the
source program is processed, this allows an immediately follow-
ing .sbttl directive to appear on the new page. The .page
source line will not appear in the file listing. Paging may be
disabled by invoking the -p directive or by using the directive:
.nlist (pag)
THE ASSEMBLER PAGE 1-21
GENERAL ASSEMBLER DIRECTIVES
If the .page directive is followed by a non zero constant or
an expression that evaluates to a non zero value then pagination
will be enabled within a false condition range to allow extended
textual information to be incorporated in the source program
with out the need to use the comment delimiter (;):
.if 0
.page 1 ;Enable pagination within 'if' block.
This text will be bypassed during assembly
but appear in the listing file.
.
.
.
.endif
1.4.6 .msg Directive
Format:
.msg /string/ or
.msg ^/string/
where: string represents a text string. The string is printed
to the console during the final assembly pass.
/ / represent the delimiting characters. These
delimiters may be any paired printing
characters, as long as the characters are not
contained within the string itself. If the
delimiting characters do not match, the .msg
directive will give the
error.
The .msg directive is useful to report assembly status or
other information during the assembly process.
THE ASSEMBLER PAGE 1-22
GENERAL ASSEMBLER DIRECTIVES
1.4.7 .error Directive
Format:
.error exp
where: exp represents an absolute expression. If the
evaluation of the expression results in a non
zero value then an
error.
The .ascii, .fcc, and .str directives place one binary byte of
data for each character in the string into the object module.
1.4.15 .ascis and .strs Directives
Format:
.ascis /string/ or
.ascis ^/string/
.strs /string/ or
.strs ^/string/
where: string is a string of printable ascii characters.
/ / represent the delimiting characters. These
delimiters may be any paired printing
characters, as long as the characters are not
contained within the string itself. If the
THE ASSEMBLER PAGE 1-26
GENERAL ASSEMBLER DIRECTIVES
delimiting characters do not match, the .ascis
and .strs directives will give the
error.
The .ascis and .strs directives place one binary byte of data
for each character in the string into the object module. The
last character in the string will have the high order bit set.
1.4.16 .asciz and .strz Directives
Format:
.asciz /string/ or
.asciz ^/string/
.strz /string/ or
.strz ^/string/
where: string is a string of printable ascii characters.
/ / represent the delimiting characters. These
delimiters may be any paired printing
characters, as long as the characters are not
contained within the string itself. If the
delimiting characters do not match, the .asciz
and .strz directive will give the
error.
The .asciz and .strz directives place one binary byte of data
for each character in the string into the object module. Fol-
lowing all the character data a zero byte is inserted to ter-
minate the character string.
THE ASSEMBLER PAGE 1-27
GENERAL ASSEMBLER DIRECTIVES
1.4.17 .assume Directive
Format:
.assume exp
where: exp represents an absolute expression. If the
evaluation of the expression results in a non
zero value then an
error if used in a relocatable program area.
The .org directive specifies that the current location counter
is to become the specified absolute value.
THE ASSEMBLER PAGE 1-34
GENERAL ASSEMBLER DIRECTIVES
1.4.25 .globl Directive
Format:
.globl sym1,sym2,...,symn
where: sym1, represent legal symbolic names.
sym2,... When multiple symbols are specified,
symn they are separated by commas.
A .globl directive may also have a label field and/or a com-
ment field.
The .globl directive is provided to export (and thus provide
linkage to) symbols not otherwise defined as global symbols
within a module. In exporting global symbols the directive
.globl J is similar to:
J == expression or J::
Because object modules are linked by global symbols, these
symbols are vital to a program. All internal symbols appearing
within a given program must be defined at the end of pass 1 or
they will be considered undefined. The assembly directive (-g)
can be invoked to make all undefined symbols global at the end
of pass 1.
The .globl directive and == construct can be overridden by a
following .local directive.
NOTE
The ASxxxx assemblers use the last occurring symbol
specification in the source file(s) as the type shown
in the symbol table and output to the .rel file.
THE ASSEMBLER PAGE 1-35
GENERAL ASSEMBLER DIRECTIVES
1.4.26 .local Directive
Format:
.local sym1,sym2,...,symn
where: sym1, represent legal symbolic names.
sym2,... When multiple symbols are specified,
symn they are separated by commas.
A .local directive may also have a label field and/or a com-
ment field.
The .local directive is provided to define symbols that are
local to the current assembly process. Local symbols are not
effected by the assembler option -a (make all symbols global).
In defining local symbols the directive .local J is similar to:
J =: expression
The .local directive and the =: construct are useful in de-
fining symbols and constants within a header or definition file
that contains many symbols specific to the current assembly pro-
cess that should not be exported into the .rel output file. A
typical usage is in the definition of SFRs (Special Function
Registers) for a microprocessor.
The .local directive and =: construct can be overridden by a
following .globl directive.
NOTE
The ASxxxx assemblers use the last occurring symbol
specification in the source file(s) as the type shown
in the symbol table and output to the .rel file.
THE ASSEMBLER PAGE 1-36
GENERAL ASSEMBLER DIRECTIVES
1.4.27 .equ, .gblequ, and .lclequ Directives
Format:
sym1 .equ expr ; equivalent to sym1 = expr
sym2 .gblequ expr ; equivalent to sym2 == expr
sym3 .lclequ expr ; equivalent to sym3 =: expr
or
.equ sym1, expr ; equivalent to sym1 = expr
.gblequ sym2, expr ; equivalent to sym2 == expr
.lclequ sym3, expr ; equivalent to sym3 =: expr
These alternate forms of equivalence are provided for user
convenience.
1.4.28 .if, .else, and .endif Directives
Format:
.if expr
. ;}
. ;} range of true condition
. ;}
.else
. ;}
. ;} range of false condition
. ;}
.endif
The conditional assembly directives allow you to include or
exclude blocks of source code during the assembly process, based
on the evaluation of the test condition.
The range of true condition will be processed if the expres-
sion 'expr' is not zero (i.e. true) and the range of false con-
dition will be processed if the expression 'expr' is zero (i.e
false). The range of true condition is optional as is the .else
directive and the range of false condition. The following are
all valid .if/.else/.endif constructions:
.if A-4 ;evaluate A-4
.byte 1,2 ;insert bytes if A-4 is
.endif ;not zero
.if K+3 ;evaluate K+3
.else
THE ASSEMBLER PAGE 1-37
GENERAL ASSEMBLER DIRECTIVES
.byte 3,4 ;insert bytes if K+3
.endif ;is zero
.if J&3 ;evaluate J masked by 3
.byte 12 ;insert this byte if J&3
.else ;is not zero
.byte 13 ;insert this byte if J&3
.endif ;is zero
All .if/.else/.endif directives are limited to a maximum nesting
of 10 levels.
The use of a .else directive outside a .if/.endif block will
generate an error. Assemblies having unequal .if and .endif
counts will cause an error.
1.4.29 .iff, .ift, and .iftf Directives
Format:
.if expr ;'if' range Condition is
;TRUE when expr is not zero
.ift ;}
. ;} range of true condition ;}
.iff ;} if
. ;} range of false condition ;} block
.iftf ;}
. ;} unconditional range ;}
.else ;'else' range Condition is
;TRUE when expr is zero
.ift ;}
. ;} range of true condition ;}
.iff ;} else
. ;} range of false condition ;} block
.iftf ;}
. ;} unconditional range ;}
.endif
The subconditional assembly directives may be placed within
conditional assembly blocks to indicate:
1. The assembly of an alternate body of code when
the condition of the block tests false.
2. The assembly of non-contiguous body of code
within the conditional assembly block,
depending upon the result of the conditional
THE ASSEMBLER PAGE 1-38
GENERAL ASSEMBLER DIRECTIVES
test in entering the block.
3. The unconditional assembly of a body of code
within a conditional assembly block.
The use of the .iff, .ift, and .iftf directives makes the use of
the .else directive redundant.
Note that the implementation of the .else directive causes
the .if tested condition to be complemented. The TRUE and FALSE
conditions are determined by the .if/.else conditional state.
All .if/.else/.endif directives are limited to a maximum
nesting of 10 levels.
The use of the .iff, .ift, or .iftf directives outside of a
conditional block results in a error code.
The use of a .else directive outside a .if/.endif block will
generate an error. Assemblies having unequal .if and .endif
counts will cause an error.
1.4.30 .ifxx Directives
Additional conditional directives are available to test the
value of an evaluated expression:
.ifne expr ; true if expr != 0
.ifeq expr ; true if expr == 0
.ifgt expr ; true if expr > 0
.iflt expr ; true if expr < 0
.ifge expr ; true if expr >= 0
.ifle expr ; true if expr <= 0
Format:
.ifxx expr
. ;}
. ;} range of true condition
. ;}
.else
. ;}
. ;} range of false condition
. ;}
.endif
THE ASSEMBLER PAGE 1-39
GENERAL ASSEMBLER DIRECTIVES
The conditional assembly directives allow you to include or
exclude blocks of source code during the assembly process, based
on the evaluation of the test condition.
The range of true condition will be processed if the expres-
sion 'expr' is not zero (i.e. true) and the range of false con-
dition will be processed if the expression 'expr' is zero (i.e
false). The range of true condition is optional as is the .else
directive and the range of false condition. The following are
all valid .ifxx/.else/.endif constructions:
.ifne A-4 ;evaluate A-4
.byte 1,2 ;insert bytes if A-4 is
.endif ;not zero
.ifeq K+3 ;evaluate K+3
.byte 3,4 ;insert bytes if K+3
.endif ;is zero
.ifne J&3 ;evaluate J masked by 3
.byte 12 ;insert this byte if J&3
.else ;is not zero
.byte 13 ;insert this byte if J&3
.endif ;is zero
All .if/.else/.endif directives are limited to a maximum nesting
of 10 levels.
The use of a .else directive outside a .if/.endif block will
generate an error. Assemblies having unequal .if and .endif
counts will cause an error.
1.4.31 .ifdef Directive
Format:
.ifdef sym
. ;}
. ;} range of true condition
. ;}
.else
. ;}
. ;} range of false condition
. ;}
.endif
THE ASSEMBLER PAGE 1-40
GENERAL ASSEMBLER DIRECTIVES
The conditional assembly directives allow you to include or
exclude blocks of source code during the assembly process, based
on the evaluation of the test condition.
The range of true condition will be processed if the symbol
'sym' has been defined with a .define directive or 'sym' is a
variable with an assigned value else the false range will be
processed. The range of true condition is optional as is the
.else directive and the range of false condition. The following
are all valid .ifdef/.else/.endif constructions:
.ifdef sym$1 ;lookup symbol sym$1
.byte 1,2 ;insert bytes if sym$1
.endif ;is defined or
;assigned a value
.ifdef sym$2 ;lookup symbol sym$2
.else
.byte 3,4 ;insert bytes if sym$1
.endif ;is not defined and
;not assigned a value
.ifdef sym$3 ;lookup symbol sym$3
.byte 12 ;insert this byte if sym$3
.else ;is defined/valued
.byte 13 ;insert this byte if sym$3
.endif ;is not defined/valued
Note that the default assembler configuration of case sensitive
means the testing for a defined symbol is also case sensitive.
All .if/.else/.endif directives are limited to a maximum
nesting of 10 levels.
The use of a .else directive outside a .if/.endif block will
generate an error. Assemblies having unequal .if and .endif
counts will cause an error.
THE ASSEMBLER PAGE 1-41
GENERAL ASSEMBLER DIRECTIVES
1.4.32 .ifndef Directive
Format:
.ifndef sym
. ;}
. ;} range of true condition
. ;}
.else
. ;}
. ;} range of false condition
. ;}
.endif
The conditional assembly directives allow you to include or
exclude blocks of source code during the assembly process, based
on the evaluation of the condition test.
The range of true condition will be processed if the symbol
'sym' is not defined by a .define directive and a variable 'sym'
has not been assigned a value else the range of false condition
will be processed. The range of true condition is optional as
is the .else directive and the range of false condition. The
following are all valid .ifndef/.else/.endif constructions:
.ifndef sym$1 ;lookup symbol sym$1
.byte 1,2 ;insert bytes if sym$1 is
.endif ;not defined and
;not assigned a value
.ifndef sym$2 ;lookup symbol sym$2
.else
.byte 3,4 ;insert bytes if sym$1
.endif ;is defined or
;is assigned a value
.ifndef sym$3 ;lookup symbol sym$3
.byte 12 ;insert this byte if sym$3
.else ;is not defined/valued
.byte 13 ;insert this byte if sym$3
.endif ;is defined/valued
All .if/.else/.endif directives are limited to a maximum nesting
of 10 levels.
The use of a .else directive outside a .if/.endif block will
generate an error. Assemblies having unequal .if and .endif
counts will cause an error.
THE ASSEMBLER PAGE 1-42
GENERAL ASSEMBLER DIRECTIVES
1.4.33 .ifb Directive
Format:
.ifb sym
. ;}
. ;} range of true condition
. ;}
.else
. ;}
. ;} range of false condition
. ;}
.endif
The conditional assembly directives allow you to include or
exclude blocks of source code during the assembly process, based
on the evaluation of the test condition.
The conditional .ifb is most useful when used in macro de-
finitions to determine if the argument is blank. The range of
true condition will be processed if the symbol 'sym' is blank.
The range of true condition is optional as is the .else direc-
tive and the range of false condition. The following are all
valid .ifb/.else/.endif constructions:
.ifb sym$1 ;argument is not blank
.byte 1,2 ;insert bytes if argument
.endif ;is blank
.ifb sym$2 ;argument is not blank
.else
.byte 3,4 ;insert bytes if argument
.endif ;is not blank
.ifb ;argument is blank
.byte 12 ;insert this byte if
.else ;argument is blank
.byte 13 ;insert this byte if
.endif ;argument not blank
All .if/.else/.endif directives are limited to a maximum nesting
of 10 levels.
The use of a .else directive outside a .if/.endif block will
generate an error. Assemblies having unequal .if and .endif
counts will cause an error.
THE ASSEMBLER PAGE 1-43
GENERAL ASSEMBLER DIRECTIVES
1.4.34 .ifnb Directive
Format:
.ifnb sym
. ;}
. ;} range of true condition
. ;}
.else
. ;}
. ;} range of false condition
. ;}
.endif
The conditional assembly directives allow you to include or
exclude blocks of source code during the assembly process, based
on the evaluation of the test condition.
The conditional .ifnb is most useful when used in macro de-
finitions to determine if the argument is not blank. The range
of true condition will be processed if the symbol 'sym' is not
blank. The range of true condition is optional as is the .else
directive and the range of false condition. The following are
all valid .ifnb/.else/.endif constructions:
.ifnb sym$1 ;argument is not blank
.byte 1,2 ;insert bytes if argument
.endif ;is not blank
.ifnb sym$2 ;argument is not blank
.else
.byte 3,4 ;insert bytes if argument
.endif ;is blank
.ifnb ;argument is blank
.byte 12 ;insert this byte if
.else ;argument is not blank
.byte 13 ;insert this byte if
.endif ;argument is blank
All .if/.else/.endif directives are limited to a maximum nesting
of 10 levels.
The use of a .else directive outside a .if/.endif block will
generate an error. Assemblies having unequal .if and .endif
counts will cause an error.
THE ASSEMBLER PAGE 1-44
GENERAL ASSEMBLER DIRECTIVES
1.4.35 .ifidn Directive
Format:
.ifidn sym$1,sym$2
. ;}
. ;} range of true condition
. ;}
.else
. ;}
. ;} range of false condition
. ;}
.endif
The conditional assembly directives allow you to include or
exclude blocks of source code during the assembly process, based
on the evaluation of the test condition.
The conditional .ifidn is most useful when used in macro de-
finitions to determine if the arguments are identical. The
range of true condition will be processed if the symbol 'sym$1'
is identical to 'sym$2' (i.e. the character strings for sym$1
and sym$2 are the same consistent with the case sensitivity
flag). When this if statement occurs inside a macro where an
argument substitution may be blank then an argument should be
delimited with the form /symbol/ for each symbol. The range of
true condition is optional as is the .else directive and the
range of false condition. The following are all valid
.ifidn/.else/.endif constructions:
.ifidn sym$1,sym$1 ;arguments are the same
.byte 1,2 ;insert bytes if arguments
.endif ;are the sane
.ifidn sym$1,sym$2 ;arguments are not the same
.else
.byte 3,4 ;insert bytes if arguments
.endif ;are not the same
.ifidn sym$3,sym$3 ;arguments are the same
.byte 12 ;insert this byte if
.else ;arguments are the same
.byte 13 ;insert this byte if
.endif ;arguments are not the same
All .if/.else/.endif directives are limited to a maximum nesting
of 10 levels.
THE ASSEMBLER PAGE 1-45
GENERAL ASSEMBLER DIRECTIVES
The use of a .else directive outside a .if/.endif block will
generate an error. Assemblies having unequal .if and .endif
counts will cause an error.
1.4.36 .ifdif Directive
Format:
.ifdif sym$1,sym$2
. ;}
. ;} range of true condition
. ;}
.else
. ;}
. ;} range of false condition
. ;}
.endif
The conditional assembly directives allow you to include or
exclude blocks of source code during the assembly process, based
on the evaluation of the test condition.
The conditional .ifdif is most useful when used in macro de-
finitions to determine if the arguments are different. The
range of true condition will be processed if the symbol 'sym$1'
is different from 'sym$2' (i.e. the character strings for sym$1
and sym$2 are the not the same consistent with the case sensi-
tivity flag). When this if statement occurs inside a macro
where an argument substitution may be blank then an argument
should be delimited with the form /symbol/ for each symbol. The
range of true condition is optional as is the .else directive
and the range of false condition. The following are all valid
.ifdif/.else/.endif constructions:
.ifdif sym$1,sym$2 ;arguments are different
.byte 1,2 ;insert bytes if arguments
.endif ;are different
.ifdif sym$1,sym$1 ;arguments are identical
.else
.byte 3,4 ;insert bytes if arguments
.endif ;are different
.ifdif sym$1,sym$3 ;arguments are different
.byte 12 ;insert this byte if
.else ;arguments are different
.byte 13 ;insert this byte if
.endif ;arguments are identical
THE ASSEMBLER PAGE 1-46
GENERAL ASSEMBLER DIRECTIVES
All .if/.else/.endif directives are limited to a maximum nesting
of 10 levels.
The use of a .else directive outside a .if/.endif block will
generate an error. Assemblies having unequal .if and .endif
counts will cause an error.
1.4.37 Alternate .if Directive Forms
Format:
.if cnd(,) arg1(, arg2)
where the cnd (followed by an optional comma) may be any of
the following:
-------------------------------------------------------
condition Assemble
(complement) Args Block if:
-------------------------------------------------------
eq ( ne ) expr equal to zero
(not equal to zero)
gt ( le ) expr greater than zero
(less than or equal to zero)
lt ( ge ) expr less than zero
(greater than or equal to zero)
def ( ndef ) symbol .define'd or user set
(not .define'd or user set)
b ( nb ) macro argument present
symbol (argument not present)
idn ( dif ) macro arguments identical
symbol (arguments not identical)
f ( t ) ----- only within a .if/.else/.endif
conditional block
tf ----- only within a .if/.else/.endif
conditional block
THE ASSEMBLER PAGE 1-47
GENERAL ASSEMBLER DIRECTIVES
All .if/.else/.endif directives are limited to a maximum nesting
of 10 levels.
The use of a .else directive outside a .if/.endif block will
generate an error. Assemblies having unequal .if and .endif
counts will cause an error.
1.4.38 Immediate Conditional Assembly Directives
The immediate conditional assembly directives allow a single
line of code to be assembled without using a .if/.else/.endif
construct. All of the previously described conditionals have
immediate equivalents.
Format:
.iif arg(,) line_to_assemble
.iifeq arg(,) line_to_assemble
.iifne arg(,) line_to_assemble
.iifgt arg(,) line_to_assemble
.iifle arg(,) line_to_assemble
.iifge arg(,) line_to_assemble
.iiflt arg(,) line_to_assemble
.iifdef arg(,) line_to_assemble
.iifndef arg(,) line_to_assemble
.iifb (,)arg(,) line_to_assemble
.iifnb (,)arg(,) line_to_assemble
.iifidn (,)arg1,arg2(,) line_to_assemble
.iifdif (,)arg1,arg2(,) line_to_assemble
.iiff line_to_assemble
.iift line_to_assemble
.iiftf line_to_assemble
Alternate Format:
.iif arg(,) line_to_assemble
.iif eq arg(,) line_to_assemble
.iif ne arg(,) line_to_assemble
.iif gt arg(,) line_to_assemble
.iif le arg(,) line_to_assemble
.iif ge arg(,) line_to_assemble
.iif lt arg(,) line_to_assemble
.iif def arg(,) line_to_assemble
.iif ndef arg(,) line_to_assemble
THE ASSEMBLER PAGE 1-48
GENERAL ASSEMBLER DIRECTIVES
.iif b (,)arg(,) line_to_assemble
.iif nb (,)arg(,) line_to_assemble
.iif idn (,)arg1,arg2(,) line_to_assemble
.iif dif (,)arg1,arg2(,) line_to_assemble
.iiff line_to_assemble
.iift line_to_assemble
.iiftf line_to_assemble
The (,) indicates an optional comma.
The .iif types b, n, idn, and dif require the commas if the
argument(s) may be blank. These commas may be removed if the
arguments are delimited with the form ^/symbol/ for each symbol.
The immediate conditional directives do not change the
.if/.else/.endif nesting level.
1.4.39 .incbin Directive
Format:
.incbin /string/ [,offset [,count]] or
.incbin ^/string/ [,offset [,count]]
where: string represents a string that is the file specifica-
tion of any file type.
/ / represent the delimiting characters. These
delimiters may be any paired printing
characters, as long as the characters are not
contained within the string itself. If the
delimiting characters do not match, the .include
directive will give the
error.
The .incbin directive is used to insert the contents of a
file verbatim into the assembler as a byte stream. This can be
handy (for example) when including some arbitrary data directly
into the executable output. However, it is recommended to use
this only for small pieces of data.
The .incbin can be invoked with one or two optional arguments
which specify the number of bytes to skip in the file and the
maximum number of bytes to insert into the output file.
THE ASSEMBLER PAGE 1-49
GENERAL ASSEMBLER DIRECTIVES
.incbin "file.dat" ; include the whole file
.incbin "file.dat",1024 ; skip the first 1024 bytes
.incbin "file.dat",1024,512 ; skip first 1024, and
; include at most 512 bytes
The ',' delimiters can be any regular delimiter - space, tab, or
','. The offset and count arguments must be local, evaluate to
a constant, and may be 0. A blank offset is by default 0 and a
blank count is the remainder of the file.
An offset equal to or greater than the file length results in
an error. A count that is larger than the remaining bytes
in a file does not result in an error.
1.4.40 .include Directive
Format:
.include /string/ or
.include ^/string/
where: string represents a string that is the file specifica-
tion of an ASxxxx source file.
/ / represent the delimiting characters. These
delimiters may be any paired printing
characters, as long as the characters are not
contained within the string itself. If the
delimiting characters do not match, the .include
directive will give the
error.
The .include directive is used to insert a source file within
the source file currently being assembled. When this directive
is encountered, an implicit .page directive is issued. When the
end of the specified source file is reached, an implicit .page
directive is issued and input continues from the previous source
file. The maximum nesting level of source files specified by a
.include directive is five.
The total number of separately specified .include files is
unlimited as each .include file is opened and then closed during
each pass made by the assembler.
The default directory path, if none is specified, for any
.include file is the directory path of the current file. For
THE ASSEMBLER PAGE 1-50
GENERAL ASSEMBLER DIRECTIVES
example: if the current source file, D:\proj\file1.asm, in-
cludes a file specified as "include1" then the file
D:\proj\include1.asm is opened.
THE ASSEMBLER PAGE 1-51
GENERAL ASSEMBLER DIRECTIVES
1.4.40.1 Including Files In Windows/DOS -
Graphical Illustration of Include File Locations
for the following command line entry:
__> bin\ascheck -l -o -s obj\prjct.rel src\prjct\prjct.asm
/-----------------------------------------------------------------------\
| (rooted) |
_____ | _____ |
| | | | | |
---| inc | <---/ ---| bin | |
| |_____| | |_____| |
| | | | |
| \___ inc4.asm | \___ ascheck.exe |
| | |
| | |
_____ | _____ _____ | _____ _____ |
| | | | | | | | | | | | (in prjct.asm directory) |
| C:\ |-----| ..\ |-----| __> |--+--| src |-----|prjct| <-------------------------------\ |
|_____| |_____| | |_____| | |_____| | |_____| | |
| | | | .include "inc1.asm" -/ |
| ^ | | \___ prjct.asm .include "C:\inc\inc4.asm" --/
| | | | \___ inc1.asm .include "..\inc\inc3.asm" -------\
Current | | | | _____ .include "src\inc\inc2.asm" -\ |
Working ------> | >---/ | | | | | |
Directory | | ---| inc | <---------------------------------------/ |
| | |_____| (relative to current working directory) |
| | | |
| | \___ inc2.asm |
| | _____ |
| | | | |
| ---| obj | |
| |_____| |
| | |
| \___ .REL, .SYM, .LST, .HLR |
| |
| _____ |
| | | (relative to current working directory) |
---| inc | <--------------------------------------------------------------------/
|_____|
|
\___ inc3.asm
THE ASSEMBLER PAGE 1-52
GENERAL ASSEMBLER DIRECTIVES
1.4.40.2 Including Files in Linux -
Graphical Illustration of Include File Locations
for the following command line entry:
__$ bin/ascheck -l -o -s obj/prjct.rel src/prjct/prjct.asm
/-----------------------------------------------------------------------\
| (rooted) |
_____ | _____ |
| | | | | |
---| inc | <---/ ---| bin | |
| |_____| | |_____| |
| | | | |
| \___ inc4.asm | \___ ascheck |
| | |
| | |
_____ | _____ _____ | _____ _____ |
| | | | | | | | | | | | (in prjct.asm directory) |
| / |-----| ../ |-----| __$ |--+--| src |-----|prjct| <-------------------------------\ |
|_____| |_____| | |_____| | |_____| | |_____| | |
| | | | .include "inc1.asm" -/ |
| ^ | | \___ prjct.asm .include "/inc/inc4.asm" ----/
| | | | \___ inc1.asm .include "../inc/inc3.asm" -------\
Current | | | | _____ .include "src/inc/inc2.asm" -\ |
Working ------> | >---/ | | | | | |
Directory | | ---| inc | <---------------------------------------/ |
| | |_____| (relative to current working directory) |
| | | |
| | \___ inc2.asm |
| | _____ |
| | | | |
| ---| obj | |
| |_____| |
| | |
| \___ .REL, .SYM, .LST, .HLR |
| |
| _____ |
| | | (relative to current working directory) |
---| inc | <--------------------------------------------------------------------/
|_____|
|
\___ inc3.asm
THE ASSEMBLER PAGE 1-53
GENERAL ASSEMBLER DIRECTIVES
1.4.41 .define and .undefine Directives
Format:
.define keyword /string/ or
.define keyword ^/string/
.undefine keyword
where: keyword is the substitutable string which must start
with a letter and may contain any combination of
digits and letters.
where: string represents a string that is substituted for the
keyword. The string may contain any sequence of
characters including white space.
/ / represent the delimiting characters. These
delimiters may be any paired printing
characters, as long as the characters are not
contained within the string itself. If the
delimiting characters do not match, the .define
directive will give the
error.
The .define directive specifies a user defined string which
is substituted for the keyword. The substitution string may it-
self contain other keywords that are substitutable. The assem-
bler resumes the parse of the line at the point the keyword was
found. Care must be excersized to avoid any circular references
within .define directives, otherwise the assembler may enter a
'recursion runaway' resulting in an
error.
The .undefine directive removes the keyword as a substitut-
able string. No error is returned if the keyword was not de-
fined.
THE ASSEMBLER PAGE 1-54
GENERAL ASSEMBLER DIRECTIVES
1.4.42 .setdp Directive
Format:
.setdp [base [,area]]
The set direct page directive has a common format in all the as-
semblers supporting a paged mode. The .setdp directive is used
to inform the assembler of the current direct page region and
the offset address within the selected area. The normal invoca-
tion methods are:
.area DIRECT (PAG)
.setdp
or
.setdp 0,DIRECT
for all the 68xx microprocessors (the 6804 has only the paged
ram area). The commands specify that the direct page is in area
DIRECT and its offset address is 0 (the only valid value for all
but the 6809 microprocessor). Be sure to place the DIRECT area
at address 0 during linking. When the base address and area are
not specified, then zero and the current area are the defaults.
If a .setdp directive is not issued the assembler defaults the
direct page to the area "_CODE" at offset 0.
The assembler verifies that any local variable used in a
direct variable reference is located in this area. Local vari-
able and constant value direct access addresses are checked to
be within the address range from 0 to 255.
External direct references are assumed by the assembler to be
in the correct area and have valid offsets. The linker will
check all direct page relocations to verify that they are within
the correct area.
The 6809 microprocessor allows the selection of the direct
page to be on any 256 byte boundary by loading the appropriate
value into the dp register. Typically one would like to select
the page boundary at link time, one method follows:
THE ASSEMBLER PAGE 1-55
GENERAL ASSEMBLER DIRECTIVES
.area DIRECT (PAG) ; define the direct page
.setdp
.
.
.
.area PROGRAM
.
ldd #DIRECT ; load the direct page register
tfr a,dp ; for access to the direct page
At link time specify the base and global equates to locate the
direct page:
-b DIRECT = 0x1000
-g DIRECT = 0x1000
Both the area address and offset value must be specified (area
and variable names are independent). The linker will verify
that the relocated direct page accesses are within the direct
page.
The preceeding sequence could be repeated for multiple paged
areas, however an alternate method is to define a non-paged area
and use the .setdp directive to specify the offset value:
.area DIRECT ; define non-paged area
.
.
.
.area PROGRAM
.
.setdp 0,DIRECT ; direct page area
ldd #DIRECT ; load the direct page register
tfr a,dp ; for access to the direct page
.
.
.setdp 0x100,DIRECT ; direct page area
ldd #DIRECT+0x100 ; load the direct page register
tfr a,dp ; for access to the direct page
The linker will verify that subsequent direct page references
are in the specified area and offset address range. It is the
programmers responsibility to load the dp register with the cor-
rect page segment corresponding to the .setdp base address
specified.
For those cases where a single piece of code must access a
defined data structure within a direct page and there are many
pages, define a dumby direct page linked at address 0. This
THE ASSEMBLER PAGE 1-56
GENERAL ASSEMBLER DIRECTIVES
dumby page is used only to define the variable labels. Then
load the dp register with the real base address but do not use a
.setdp directive. This method is equivalent to indexed address-
ing, where the dp register is the index register and the direct
addressing is the offset.
1.4.43 .16bit, .24bit, and .32bit Directives
Format:
.16bit ;specify 16-bit addressing
.24bit ;specify 24-bit addressing
.32bit ;specify 32-bit addressing
The .16bit, .24bit, and .32bit directives are special direc-
tives for assembler configuration when default values are not
used.
1.4.44 .msb Directive
Format:
.msb n
The .msb directive is only available in selected assemblers
which support 24 or 32-bit addressing.
The assembler operator '>' selects the upper byte (MSB) when
included in an assembler instruction. The default assembler
mode is to select bits <15:8> as the MSB. The .msb directive
allows the programmer to specify a particular byte as the 'MSB'
when the address space is larger than 16-bits.
The assembler directive .msb n configures the assembler to
select a particular byte as MSB. Given a 32-bit address of MNmn
(M(3) is <31:24>, N(2) is <23:16>, m(1) is <15:8>, and n(0) is
<7:0>) the following examples show how to select a particular
address byte:
.msb 1 ;select byte 1 of address
; Questionable syntax: missing or improper operators,
terminators, or delimiters.
String Substitution / recursion error.
Undefined symbol encountered during assembly.
errors. Those assemblers updated to pro-
vide the expanded error messages will show three lines on the
stdout device as shown by this error:
?ASxxxx-Error- in line 1867 of tez80e.asm
'1867 ld.l sp,(var1) ;a'
Only .SIS and .LIL suffixes allowed.
The first line is the basic error in line xxxx message. The
second line lists the actual line in error followed by a third
line containing the more specific error.
The listing file (.lst) will have the first and third lines
of the error message inserted preceeding the line containing the
error.
1.7 LISTING FILE
The (-l) option produces an ascii output listing file. Each
page of output contains a five line header:
1. The ASxxxx program name and page number
2. Assembler Radix and Address Bits
THE ASSEMBLER PAGE 1-64
LISTING FILE
3. Title from a .title directive (if any)
4. Subtitle from a .sbttl directive (if any)
5. Blank line
Each succeeding line contains six fields:
1. Error field (first two characters of line)
2. Current location counter
3. Generated code in byte format
4. Opcode cycles count
5. Source text line number
6. Source text
The error field may contain upto 2 error flags indicating any
errors encountered while assembling this line of source code.
The current location counter field displays the 16-bit,
24-bit, or 32-bit program position. This field will be in the
selected radix.
The generated code follows the program location. The listing
radix determines the number of bytes that will be displayed in
this field. Hexadecimal listing allows six bytes of data within
the field, decimal and octal allow four bytes within the field.
If more than one field of data is generated from the assembly of
a single line of source code, then the data field is repeated on
successive lines.
The opcode cycles count is printed within the delimiters [ ]
on the line with the source text. This reduces the number of
generated code bytes displayed on the line with the source list-
ing by one. (The -c option disables all opcode cycle listing.)
The source text line number is printed in decimal and is fol-
lowed by the source text. A Source line with a .page directive
is never listed. (The -u option overrides this behavior.)
THE ASSEMBLER PAGE 1-65
LISTING FILE
Two additional options are available for printing the source
line text. If the -b option is specified then the listed source
line contains all the .define substitutions. If the -bb option
is specified then the original source line is printed before the
source line with substitutions.
Two data field options are available to flag those bytes
which will be relocated by the linker. If the -f option is
specified then each byte to be relocated will be preceeded by
the '`' character. If the -ff option is specified then each
byte to be relocated will be preceeded by one of the following
characters:
1. * paged relocation
2. u low byte of unsigned word or unsigned byte
3. v high byte of unsigned word
4. p PCR low byte of word relocation or PCR byte
5. q PCR high byte of word relocation
6. r low byte relocation or byte relocation
7. s high byte relocation
Assemblers which use 24-bit or 32-bit addressing use an ex-
tended flagging mode:
1. * paged relocation
2. u 1st byte of unsigned value
3. v 2nd byte of unsigned value
4. U 3rd byte of unsigned value
5. V 4th byte of unsigned value
6. p PCR 1st byte of relocation value or PCR byte
7. q PCR 2nd byte of relocation value
8. P PCR 3rd byte of relocation value
9. Q PCR 4th byte of relocation value
THE ASSEMBLER PAGE 1-66
LISTING FILE
10. r 1st byte of relocation value or byte relocation
11. s 2nd byte of relocation value
12. R 3rd byte of relocation value
13. S 4th byte of relocation value
1.8 SYMBOL TABLE FILE
The symbol table has two parts:
1. The alphabetically sorted list of symbols and/or labels
defined or referenced in the source program.
2. A list of the program areas defined during assembly of
the source program.
The sorted list of symbols and/or labels contains the follow-
ing information:
1. Program area number (none if absolute value or exter-
nal)
2. The symbol or label
3. Directly assigned symbol is denoted with an (=) sign
4. The value of a symbol, location of a label relative to
the program area base address (=0), or a **** indicat-
ing the symbol or label is undefined.
5. The characters: G - global, L - local,
R - relocatable, and X - external.
The list of program areas provides the correspondence between
the program area numbers and the defined program areas, the size
of the program areas, and the area flags (attributes).
THE ASSEMBLER PAGE 1-67
OBJECT FILE
1.9 OBJECT FILE
The object file is an ascii file containing the information
needed by the linker to bind multiple object modules into a com-
plete loadable memory image. The object module contains the
following designators:
[XDQ][HL][234]
X Hexadecimal radix
D Decimal radix
Q Octal radix
H Most significant byte first
L Least significant byte first
2 16-Bit Addressing
3 24-Bit Addressing
4 32-Bit Addressing
H Header
M Module
G Merge Mode
B Bank
A Area
S Symbol
T Object code
R Relocation information
P Paging information
Refer to the linker for a detailed description of each of the
designators and the format of the information contained in the
object file.
1.10 HINT FILE
The hint file is an ascii file containing information needed
by the linker to convert the listing file into a relocated list-
ing file. Each line in the .hlr file coresponds to a single
line in the listing file. The text line usually contains 3 or 4
parameters in the radix selected for the assembler as shown in
the following table:
Line Position: 123456789012
------------
Octal: 111 222 333
Decimal: 111 222 333
THE ASSEMBLER PAGE 1-68
HINT FILE
Hex: 11 22 33
Parameter 1 specifies the parameters listed in the line.
A bit is set for each listing option enabled during the
assembly of the line.
BIT 0 - LIST_ERR Error Code(s)
BIT 1 - LIST_LOC Location
BIT 2 - LIST_BIN Generated Binary Value(s)
BIT 3 - LIST_EQT Assembler Equate Value
BIT 4 - LIST_CYC Opcode Cycles
BIT 5 - LIST_LIN Line Numbers
BIT 6 - LIST_SRC Assembler Source Code
BIT 7 - HLR_NLST Listing Inhibited
Parameter 2 is the internal assembler listing mode
value specified for this line during the assembly process:
0 - NLIST No listing
1 - SLIST Source only
2 - ALIST Address only
3 - BLIST Address only with allocation
4 - CLIST Code
5 - ELIST Equate only
6 - ILIST IF conditional evaluation
Parameter 3 is the number of output bytes listed
for this line.
The 4th parameter is only output if an equate references a
value in a different area. The area name is output in the fol-
lowing format following the 3 parameters described above:
Line Position: 123456789012
------------
Area Name: equatearea
When the line number is output to the .hlr file (-r option)
the line number is prepended to the 3 or 4 parameters described
above. The line number is always in decimal in the following
format:
Line Position: 1234567
-------
Decimal: LLLLL
Thus the four formats (for each radix) that may be present in
a .hlr file are:
THE ASSEMBLER PAGE 1-69
HINT FILE
Line Position: 123456789012345678901234567890
------------------------------
11 22 33
11 22 33 equatearea
LLLLL 11 22 33
LLLLL 11 22 33 equatearea
The linker understands these formats without any user inter-
action.
CHAPTER 2
THE MACRO PROCESSOR
2.1 DEFINING MACROS
By using macros a programmer can use a single line to insert
a sequence of lines into a source program.
A macro definition is headed by a .macro directive followed
by the source lines. The source lines may optionally contain
dummy arguments. If such arguments are used, each one is listed
in the .macro directive.
A macro call is the statement used by the programmer to call
the macro source program. It consists of the macro name fol-
lowed by the real arguments needed to replace the dummy argu-
ments used in the macro.
Macro expansion is the insertion of the macro source lines
into the main program. Included in this insertion is the
replacement of the dummy arguments by the real arguments.
Macro directives provide a means to manipulate the macro ex-
pansions. Only one directive is allowed per source line. Each
directive may have a blank operand field or one or more
operands. Legal operands differ with each directive. The
macros and their associated directives are detailed in this
chapter.
Macro directives can replace any machine dependent mnemonic
associated with a specific assembler. However, the basic assem-
bler directives cannot be replaced with a macro.
THE MACRO PROCESSOR PAGE 2-2
DEFINING MACROS
2.1.1 .macro Directive
Format:
[label:] .macro name, dummy argument list
where: label represents an optional statement label.
name represents the user-assigned symbolic
name of the macro. This name may be
any legal symbol and may be used as a
label elsewhere in the program. The
macro name is not case sensitive,
name, NAME, or nAmE all refer to the
same macro.
, represents a legal macro separator
(comma, space, and/or tab).
dummy represents a number of legal symbols
argument that may appear anywhere in the body of
list the macro definition, even as a label.
These dummy symbols can be used elsewhere
in the program with no conflict of
definition. Multiple dummy arguments
specified in this directive may be
separated by any legal separator. The
detection of a duplicate or an illegal
symbol in a dummy argument list
terminates the scan and causes a
error to be generated.
A comment may follow the dummy argument list in a .macro direc-
tive, as shown below:
.macro abs a,b ;Defines macro abs
The first statement of a macro definition must be a .macro
directive. Defining a macro with the same name as an existing
macro will generate an
error is generated. If fewer arguments appear in the
macro call than in the macro definition, missing arguments are
assumed to be null values. The conditional directives .if b and
.if nb can be used within the macro to detect missing arguments.
The number of arguments can be determined using the .narg direc-
tive.
2.3.5 Creating Local Symbols Automatically
A label is often required in an expanded macro. In the con-
ventional macro facilituies thus far described, a label must be
explicitly specified as an argument with each macro call. The
user must be careful in issuing subsequent calls to the same
macro in order avoid duplicating labels. This concern can be
eliminated through a feature of the ASxxxx macro facility that
creates a unique symbol where a label is required in an expanded
macro.
ASxxxx allows temporary symbols of the form n$, where n is a
decimal integer. Automatically created symbols are created in
numerical order beginning at 10000$.
The automatic generation of local symbols is invoked on each
call of a macro whose definition contains a dummy argument pre-
ceded by the question mark (?) character, as shown in the macro
definition below:
.macro beta a,?b ;dummy argument b with ?
tst a
beq b
add #5,a
b:
.endm
A local symbol is created automatically only when a real ar-
gument of the macro call is either null or missing, as shown in
Example 1 below. If the real argument is specified in the macro
call, however, generation of the local symbol is inhibited and
normal argument replacement occurs, as shown in Example 2 below.
(Examples 1 and 2 are both expansions of the beta macro defined
above.)
THE MACRO PROCESSOR PAGE 2-10
ARGUMENTS IN MACRO DEFINITIONS AND MACRO CALLS
Example 1: Create a Local Symbol for the Missing Argument
beta flag ;Second argument is missing.
tst flag
beq 10000$ ;Local symbol is created.
add #5,flag
10000$:
Example 2: Do Not Create a Local Symbol
beta r3,xyz
tst r3
beq xyz
add #5,r3
xyz:
Automatically created local symbols resulting from the expan-
sion of a macro, as described above, do not establish a local
symbol block in their own right.
When a macro has several arguments earmarked for automatic
local symbol generation, substituting a specific label for one
such argument risks assembly errors because the arguments are
constructed at the point of macro invocation. Therefor, the ap-
pearance of a label in the macro expansion will create a new lo-
cal symbol block. The new local symbol block could leave local
symbol references in the previous block and their symbol defini-
tions in the new one, causing error codes in the assembly list-
ing. Furthermore a later macro expansion that creates local
symbols in the new block may duplicate one of the symbols in
question, causing an additional error code
error.
The .narg directive is used to determine the number of arguments
in the macro call currently being expanded. Hence, the .narg
directive can appear only within a macro definition; if it ap-
pears elsewhere, an
error.
, represents any legal separator (comma,
space, and/or tab).
string represents a string of printable 7-bit
ascii characters. If the character
string contains a legal separator
(comma, space and/or tab) the whole
string must be delimited using the
up-arrow (^) construct ^/ /.
If the delimiting characters do not
match or if the ending delimiter
cannot be detected because of a
syntactical error in the character
string, the .nchr directive reports
a
error.
The .nchr directive, which can appear anywhere in an ASxxxx pro-
gram, is used to determine the number of characters in a speci-
fied character string. This directive is useful in calculating
the length of macro arguments.
THE MACRO PROCESSOR PAGE 2-14
MACRO ATTRIBUTE DIRECTIVES
2.4.3 .ntyp Directive
Format:
[label:] .ntyp symbol,arg
where: label represents an optional statement label.
symbol represents any legal symbol. The symbol
is made absolute and equated to 0 if
arg is an absolute value or a non
relocatable symbol. The symbol is made
absolute and equated to 1 if arg is a
relocatable symbol. If a symbol is not
specified then the .ntyp directive is
flagged with a
error.
, represents any legal separator (comma,
space, and/or tab).
arg represents any legal expression or
symbol. If arg is not specified
then the .ntyp directive is flagged
with a
error.
The .ntyp directive, which can appear anywhere in an ASxxxx pro-
gram, is used to determine the symbol or expression type as ab-
solute (0) or relocatable (1).
THE MACRO PROCESSOR PAGE 2-15
MACRO ATTRIBUTE DIRECTIVES
2.4.4 .nval Directive
Format:
[label:] .nval symbol,arg
where: label represents an optional statement label.
symbol represents any legal symbol. The symbol
is equated to the value of arg and made
absolute. If a symbol is not specified
then the .nval directive is flagged
with a
error.
, represents any legal separator (comma,
space, and/or tab).
arg represents any legal expression or
symbol. If arg is not specified
then the .nval directive is flagged
with a
error.
The .nval directive, which can appear anywhere in an ASxxxx pro-
gram, is used to determine the value of arg and make the result
an absolute value.
2.5 INDEFINITE REPEAT BLOCK DIRECTIVES
An indefinite repeat block is similar to a macro definition
with only one dummy argument. At each expansion of the inde-
finite repeat range, this dummy argument is replaced with suc-
cessive elements of a real argument list. Since the repeat
directive and its associated range are coded in-line within the
source program, this type of macro definition and expansion does
not require calling the macro by name, as required in the expan-
sion of the conventional macros previously described.
An indefinite repeat block can appear within or outside
another macro definition, indefinite repeat block, or repeat
block. The rules specifying indefinite repeat block arguments
are the same as for specifying macro arguments.
THE MACRO PROCESSOR PAGE 2-16
INDEFINITE REPEAT BLOCK DIRECTIVES
2.5.1 .irp Directive
Format:
[label:] .irp sym,argument_list
.
.
(range of indefinite repeat block)
.
.
.endm
where: label represents an optional statement label.
sym represents a dummy argument that is
replaced with successive real arguments
from the argument list. If the dummy
argument is not specified, the .irp
directive is flagged with a
error.
, represents any legal separator (comma,
space, and/or tab).
argument_list represents a list of real arguments
that are to be used in the expansion
of the indefinite repeat range. A real
argument may consist of one or more
7-bit ascii characters; multiple
arguments must be separated by any
legal separator (comma, space, and/or
tab). If an argument must contain
a legal separator then the up-arrow
(_^) construct is require for that
argument. If no real arguments are
specified, no action is taken.
range represents the block of code to be
repeated once for each occurrence of
a real argument in the list. The
range may contain other macro
definitions, repeat ranges and/or
the .mexit directive.
.endm indicates the end of the indefinite
repeat block range.
The .irp directive is used to replace a dummy argument with suc-
cessive real arguments specified in an argument list. This
THE MACRO PROCESSOR PAGE 2-17
INDEFINITE REPEAT BLOCK DIRECTIVES
replacement process occurrs during the expansion of an inde-
finite repeat block range.
2.5.2 .irpc Directive
Format:
[label:] .irpc sym,string
.
.
(range of indefinite repeat block)
.
.
.endm
where: label represents an optional statement label.
sym represents a dummy argument that is
replaced with successive real characters
from the argument string. If the dummy
argument is not specified, the .irpc
directive is flagged with a
error.
, represents any legal separator (comma,
space, and/or tab).
string represents a list of 7-bit ascii
characters. If the string contains
legal separator characters (comma,
space, and/or tab) then the up-arrow
(_^) construct must delimit the string.
range represents the block of code to be
repeated once for each occurrence of
a real argument in the list. The
range may contain other macro
definitions, repeat ranges and/or
the .mexit directive.
.endm indicates the end of the indefinite
repeat block range.
The .irpc directive is available to permit single character sub-
stition. On each iteration of the indefinite repeat range, the
dummy argument is replaced with successive characters in the
specified string.
THE MACRO PROCESSOR PAGE 2-18
INDEFINITE REPEAT BLOCK DIRECTIVES
2.6 REPEAT BLOCK DIRECTIVE
A repeat block is similar to a macro definition with only one
argument. The argument specifies the number of times the repeat
block is inserted into the assembly stream. Since the repeat
directive and its associated range are coded in-line within the
source program, this type of macro definition and expansion does
not require calling the macro by name, as required in the expan-
sion of the conventional macros previously described.
A repeat block can appear within or outside another macro de-
finition, indefinite repeat block, or repeat block.
2.6.1 .rept Directive
Format:
[label:] .rept exp
.
.
(range of repeat block)
.
.
.endm
where: label represents an optional statement label.
exp represents any legal expression.
This value controls the number of
times the block of code is to be assembled
within the program. When the expression
value is less than or equal to zero (0),
the repeat block is not assembled. If
this value is not an absolute value, the
.rept directive is flagged with an
errors.
(8) Fixed bug in macro processor related to
missing or malformed arguments.
(9) Update sections of code using strncpy() giving
errors when compiled with GCC 10.2.0 (no other
RELEASE NOTES Page D-2
compiler flagged this code with an error).
2019_03_10 Version 5.30 Update 1
This update for Version 5.30 of the ASxxxx Cross
Assemblers includes fixes for the following errors:
(1) The as78k0 assembler had numerous register
'H' and 'L' errors which have been corrected.
(2) The linker reported the wrong version and has
been corrected.
January 2019 Version 5.3
(1) Added new assemblers:
as78k0, as8008, as8008s, as8x300, and asz280
(2) General assembler updates
added -i to insert assember lines before input files
fixed .macro listing options
fixes related to
errors and the -bb option
fix the escape processing of the '\' character
.include file location illustrations
(3) General linker updates
fix library path file strings
rewrite of .lst to .rst translation
(4) Assembler specific fixes
as740
changed 2-byte code to 1-byte code definition
as8048
Corrected bug in "sel" instruction in .8041 mode.
asf2mc
Corrected documentation for asf2mc processor types.
aspic
Fixed missing machine type variable definition
Fixed 'tris' instruction
asst8
Included add/addw/sub/subw sp,#byte modes.
Added the int opcode. Cleaned up st8addr.c
addressing mode comments and code.
RELEASE NOTES Page D-3
January 2017 Version 5.20
(1) Completed the functionality for propagating
the boundary specifications .odd, .even, and
.bndry processed during assembly to the linker.
(2) Restored the correct functionality of the
.org directive in areas of REL type.
(3) Added Intel Hex legacy start address record
type 1 as an option.
Summary of changes/additions to the ASxxxx Assemblers from Ver-
sion 5.11 to Version 4.11.
2015_06_27 Version 5.10 Update 1
This update for Version 5.10 of the ASxxxx Cross
Assemblers includes fixes for the following errors:
(1) The as6500 assembler incorrectly assembled
cpx # and cpy # instructions.
(2) An error in asmain.c inhibited the listing of
all .if.. assembly directives.
2014_10_31 Version 5.10
(1) Rewrite of listing to relocated listing translation
code in the assembler and the linker base code.
The Assemblers now create a .lst to .rst hint file
with the extension .hlr (when both .lst and .rel
files are created by the assembler).
(2) Add as6100 assembler (Intersil IM6100 / Harris HM6100)
(3) Add as78k0s assembler (Renesas/NEC 78K/0S)
2013_05_12 Version 5.00 Update 6
RELEASE NOTES Page D-4
This update for Version 5.00 of the ASxxxx Cross
Assemblers rolls up updates 1, 2, 3, 4, and 5 with fixes
for the following:
(1) Fix asscmp assembler (pre-increment on fetch).
(2) Fix aslink error reporting for PC relative modes.
2012_08_01 Version 5.00 Update 5
Update_05 for the ASxxxx Assembler and Linker Version 5.00
(use 'pkunzip -d u05500.zip' for extraction with MS-DOS)
(use 'unzip -L -a u05500.zip' for extraction with Linux)
See the note about merging
this update with the
asxv5pxx distribution.
This update for Version 5.00 of the ASxxxx Cross
Assemblers rolls up updates 1, 2, 3, and 4 with the addition of
a new assembler and fixes:
(1) A new cross assembler for the Fairchild
F8 microprocessor (or Mostek 3870).
(2) Minor syntactical changes for ANSI C compatability,
fix type conversion warnings, and update the
various build, make, and test files.
Update 4 Items
(1) The AS8048 base opcode value for the JMPP
instruction should be B3 and NOT 83.
(2) The AS8051 assembler calculates incorrect
offsets when using the program counter, ".",
as a destination in the instructions having
a PC-Relative addressing mode. These
instructions include: jbc, jb, jbn, jc,
jnc, jz, jnz, cjne, and djnz.
Update 3 Items
(1) A new cross assembler for the Fairchild
RELEASE NOTES Page D-5
F8 microprocessor (or Mostek 3870).
(2) Minor syntactical changes for ANSI C compatability,
fix type conversion warnings, and update the
various build, make, and test files.
(3) New cross assemblers for STMicroelectronics
ST6, ST7, and STM8 microprocessors.
(4) An ASlink list file update error fix (-u option)
causing some errors not to be inserted into the
created .rst file.
(5) An additional ASxxxx assembler option (-v) which
enables checking for out of range signed / unsigned
values in symbol equates and arithmetic operations.
This option has some ambiguities as internally the
assemblers use unsigned arithmetic for calculations.
(e.g. for a 2-byte machine -32768 and 32768 are both
represented as 0x8000)
Update 2 Items
(1) When using the assembler directive .end to specify
the code entry address the assembler fails to set
the variable .__.END. as a global. Therefor the
value of .__.END. is not passed to the linker and
the start address frame is always zero.
(2) The linker will fail to create a start address frame
when there is no code generated within the area/bank
referenced by the .__.END. variable.
Update 1 Items
(1) The newest versions of gcc (and perhaps other
compilers) give warnings about missing arguments
in the fprintf() function. This update replaces
fprintf(arg1, arg2) with fprintf(arg1, "%s", arg2)
in each affected line of code.
(2) The newest versions of gcc (and perhaps other
compilers) have defined 'getline' as a standard
function in 'stdio.h'. This conflicts with the
function 'getline()' in the ASxxxx package.
All references to 'getline()' have been changed
to 'nxtline()'.
RELEASE NOTES Page D-6
Before merging the asxv5pxx directory and subdirectories with
the V5.00 distribution the following files/directories must be
deleted:
[asxv5pxx\asf2mc8\f8mch.c
[asxv5pxx\asf2mc8\f8adr.c
[asxv5pxx\asf2mc8\f8pst.c
[asxv5pxx\asf2mc8\f8.h
[asxv5pxx\asxmak\vc6\asf2mc8]
[asxv5pxx\asxmak\vs05\asf2mc8]
2011_07_24 Version 5.00 Update 4
This update for Version 5.00 of the ASxxxx Cross
Assemblers includes fixes for the following errors:
(1) The AS8048 base opcode value for the
JMPP instruction should be B3 and NOT 83.
(2) The AS8051 assembler calculates incorrect
offsets when using the program counter, ".",
as a destination in the instructions having
a PC-Relative addressing mode. These
instructions include: jbc, jb, jbn, jc,
jnc, jz, jnz, cjne, and djnz.
2010_10_31 Version 5.00 Update 3
This update for Version 5.00 of the ASxxxx Cross
Assemblers rolls up updates 1 and 2 with the addition of
three new assemblers and fixes:
(1) New cross assemblers for STMicroelectronics
ST6, ST7, and STM8 microprocessors.
(2) An ASlink list file update error fix (-u option)
causing some errors not to be inserted into the
created .rst file.
(3) An additional ASxxxx assembler option (-v) which
enables checking for out of range signed / unsigned
values in symbol equates and arithmetic operations.
RELEASE NOTES Page D-7
This option has some ambiguities as internally the
assemblers use unsigned arithmetic for calculations.
(e.g. for a 2-byte machine -32768 and 32768 are both
represented as 0x8000)
Update 2 Items
(1) When using the assembler directive .end to specify
the code entry address the assembler fails to set
the variable .__.END. as a global. Therefor the
value of .__.END. is not passed to the linker and
the start address frame is always zero.
(2) The linker will fail to create a start address frame
when there is no code generated within the area/bank
referenced by the .__.END. variable.
Update 1 Items
(1) The newest versions of gcc (and perhaps other
compilers) give warnings about missing arguments
in the fprintf() function. This update replaces
fprintf(arg1, arg2) with fprintf(arg1, "%s", arg2)
in each affected line of code.
(2) The newest versions of gcc (and perhaps other
compilers) have defined 'getline' as a standard
function in 'stdio.h'. This conflicts with the
function 'getline()' in the ASxxxx package.
All references to 'getline()' have been changed
to 'nxtline()'.
2010_04_01 Version 5.00 Update 2
This update for Version 5.00 of the ASxxxx Cross
Assemblers includes fixes for the following errors:
(1) When using the assembler directive .end to specify
the code entry address the assembler fails to set
the variable .__.END. as a global. Therefor the
value of .__.END. is not passed to the linker and
the start address frame is always zero.
(2) The linker will fail to create a start address frame
when there is no code generated within the area/bank
RELEASE NOTES Page D-8
referenced by the .__.END. variable.
2010_03_03 Version 5.00 Update 1
This update for Version 5.00 of the ASxxxx Cross
Assemblers includes fixes for the following errors:
(1) The newest versions of gcc (and perhaps other
compilers) give warnings about missing arguments
in the fprintf() function. This update replaces
fprintf(arg1, arg2) with fprintf(arg1, "%s", arg2)
in each affected line of code.
(2) The newest versions of gcc (and perhaps other
compilers) have defined 'getline' as a standard
function in 'stdio.h'. This conflicts with the
function 'getline()' in the ASxxxx package.
All references to 'getline()' have been changed
to 'nxtline()'.
2009_04_01 (Version 5.00)
Added a general purpose macro processor to the ASxxxx assem-
blers.
Added true (t), false (f), and true or false (tf) condition-
als to the .if / .else / .endif construct. The conditionals
.ift, .iff, and .iftf allow replacement of the .else directive
making the .if / .endif construct more readable.
e.g. .ift if condition is true
An alternate .if construction has been added to the ASxxxx
assemblers:
e.g. .if eq,... if argument == 0
The immediate conditional statements have been added to the
ASxxxx assemblers. These conditionals can replace the
.if / ... / .endif construct for a single assembler source line:
RELEASE NOTES Page D-9
e.g. .iifeq arg label: .word 0x1234
The alternate immediate conditional statements have also been
added to the ASxxxx assemblers:
e.g. .iif eq,arg label: .word 0x1234
The listing options for the ASxxxx assemblers has been up-
dated to enable/disable any of the following parameters from be-
ing output to a generated listing file:
err error codes
loc code location
bin assembler binary code
eqt symbolic equates / if evaluations
cyc machine cycles
lin assembler source line number
src assembler source code
pag paging control
lst listing of .list / .nlist
md macro definition
me macro expansion
meb macro expansion binary code
! sets the listing mode to
!(.list) or !(.nlist) before
applying the sublist options
e.g. .nlist (lst,pag) ; disable .list/.nlist listing
; and pagination
The NOT parameter, !, is used to set the listing mode to the
opposite sense of the .list or .nlist directive. For example:
.nlist (!) is equivalent to .list and
.list (!) is equivalent to .nlist
To enable listing and simultaneously disable the cycle count use
the directive:
.nlist (!,cyc)
or if you wish to suppress the listing of the .list / .nlist
directives:
.nlist ; disables all listing
RELEASE NOTES Page D-10
.nlist (!,lst) ; enables all listing except
: .list (...) and .nlist
Normally the .list and .nlist directives are not evaluated
when encountered within a FALSE conditional block. This default
behavior can be modified by specifying a non zero argument in
the .list or .nlist directive:
.nlist 1,(!,lst) ; enables listing even within
; a FALSE conditional block
The .bndry assembler directive has been added to ASxxxx. The
.bndry directive changes the current location address to be
evenly divisible by a specified integer value.
e.g. .org 0
.bndry 4
; . == 0
.org 1
.bndry 4
; . == 4
2009_02
Added the Cypress PSoc (M8C) ASM8C assembler
to ASxxxx.
2008_09
Added the 8048 (8021, 8022, and 8041) AS8048
assembler to Asxxxx.
2008_02
Added the SC/MP ASSCMP assembler to ASxxxx.
RELEASE NOTES Page D-11
2008_02_03 (Version 4.11 Update 4)
An update to the AS2650 assembler to
fix the following errors:
1) The indexed addressing mode generates invalid
code by using the first argument register as
the index register: (addr = 0x1234)
loda r0,[addr,r1] 0C F2 34
this should give 0D F2 34
2) The index addressing mode did not generate
an addressing error when the first argument
register was not r0:
stra r1,[addr,r2] should give an
error, the source must be r0
loda r2,[addr,r3] should give an
error, the destination must be r0
3) The S2650 auto increment and decrement indexing
modes always perform the register update before
the register is used. i.e. +Rn or -Rn. The
assembler now accepts +Rn or Rn+ as meaning
pre-increment and -Rn or Rn- as meaning
pre-decrement.
The AS2650 assembler tstscn files have been updated
for testing the assemblers.
2007_10_21 (Version 4.11 Fix)
In the AS6816 assembler the instruction ANDP gives
wrong object code. Changed from 37 2A to 37 3A.
RELEASE NOTES Page D-12
2007_04_01 (Version 4.11 Update 3)
An update to the ASPIC assembler and
associated fix to ASLINK:
1) Change the pic addressing to lo/hi from hi/lo
byte ordering.
2) The update fixes an error in the pic17 series
LCALL instruction.
3) A rewrite of the pic18 series assembler to change
the PC addressing from 1 per 16-bit word to 1 per
8-bit byte and add the extended instruction set.
4) Modify the Linker Merge Mode processing to take into
account the discarded low order bits for PC Relative
Addressing.
5) New tstscn files for testing the assemblers.
2006_11_01 (Version 4.11 Optional Update 2)
1) OS9 definition files and an OS9 assembler module
which creates the OS9 header, code and data areas,
and the module CRC block:
os9_mod.def OS9 Module Definitions
os9_sys.def OS9 Sytem Definitions
os9_mod.asm OS9 Module Begin / End Code
2) a program, s19os9, to post-process assembled OS9
modules in S19 format into binary OS9 modules
with the appropriate header checksum and module
CRC values calculated.
3) new make and project files which may be used to
compile the s19os9 program.
RELEASE NOTES Page D-13
2006_11_01 (Version 4.11 Optional Update 01)
The .list and .nlist directives are now modified
by .if / .else / .endif processing so that they are
active only in a TRUE clause.
The .page and .include directives are now modified
by the .list and .nlist directives so that pagination
occurs only when listing is active.
The new default functionality for the .list, .nlist
and .page directives may be modified by including an
optional argument in the directive as shown here for
the the .list directive:
.list arg
a non-zero argument invokes the directive irrespective
of the .if / .else / .endif status.
2006_07_26 (Version 4.11 Patch 01)
The assembly of a direct page instruction with a
numeric constant causes a program crash when a .rel
file is created. e.g.:
andb *0x02
The use of a symbolic constant or symbol plus a
a constant compiles normally.
val = 0x02
andb *val
andb *extern+0x01
The assemblers effected are:
as6809
as6812
ash8
aspic
RELEASE NOTES Page D-14
Summary of changes/additions to the ASxxxx Assemblers from
Version 4.10 to Version 4.11.
1. Incorporated the patches contained in p01410.zip which
corrected a coding error that affected BANKS containing
multiple ABS areas or mixed AREA types.
2. Incorporated the patches contained in p02410.zip which
corrected improper use of R_USGN in most addressing
modes in AS6500. This caused unexpected errors in
V4.xx because of the ASxxxx core change to 32-bit in-
tegers and arithmetic.
3. Incorporated the patches contained in p03410.zip which
corrected errors in the .local and .globl assembler
directive processing routine that introduced unwanted
side effects for variable and symbol definition files.
These effects included improper definitions and incor-
rect error warnings.
4. The following new subdirectories and their files have
been added to the asxtst directory:
* areabank Area and Bank Processing Test
This directory contains several test programs:
ts.asm (single file - multiple areas), tm1.asm and
tm2.asm (multiple file - multiple areas), and
tbm.asm, tbm1.asm, and tbm2.asm ( multiple file -
multiple areas within a bank) and several other
files which verify the correct operation of the
linker when used with a single linked file, multi-
ple linked files having no banking, and multiple
linked files with banking. These reference files
show in detail how the .area and .bank directives
work together.
* equtst Equate Processing Test
This directory contains a test file for verifying
the operation of the .globl, .local, .equ, .gblequ,
and .lclequ directives and the =, ==, and =:
equalities.
* inctst Nested Include File Test
* itst Include File Error Reporting Test
RELEASE NOTES Page D-15
5. Incorporated the updates contained in u01410.zip which
added 10 undocumented 8085 instructions to the AS8085
assembler.
Summary of changes/additions to the ASxxxx Assemblers from
Version 4.00 to Version 4.10.
1. Added new assemblers for the Zilog EZ80, Zilog Z8, Sig-
netics 2650, and Fujitsu F2MC8(L,FX) processors.
2. Added the processor cycle count option (-c) to all pro-
cessors.
3. Several of the assemblers (ASZ80, ASRAB, AS6805,
AS6808, AS6812, ASF2MC8, ...) now support subsets or
supersets of their basic opcodes by the use of assem-
bler specific directives.
4. Added .ifeq, .ifne, .iflt, .ifgt, .ifle, and .ifge con-
ditional assembly directives.
5. Added support for the Tandy Color Computer Disc Basic
binary file format to ASLINK.
6. Problem:
When an area size is equal to the 'address space size'
the size parameter is reported as 0. (A normal condi-
tion caused by address rollover to 0.) Aslink inter-
preted this as a 0 size.
Fix:
A new area 'Output Code Flag' bit was defined to indi-
cate when data is defined in an area. ASxxxx and
Aslink have been updated to set and process this area
flag bit.
7. Problem:
The use of the .end assembler directive in an Asxxxx
assembler would cause Aslink to output the optional
start address in all output files.
Fix:
Updated Aslink to output the optional start address
only in the output file associated with the area/bank
RELEASE NOTES Page D-16
containing the .end directive.
8. Problem:
Aslink creates output files for banks with no output
data.
Fix:
Aslink now deletes any created output file for banks
with no data.
9. Incorporated the patches contained in p01400.zip for
files t1802.asm and 1802pst.c to correct for an error
in the opcodes generated for the BM, BL, and BNF
mnemonics.
10. Incorporated the patches contained in p02400.zip for
file ds8adr.c to correct for an error in the direct
page addressing mode of AS8xCxxx.
11. Incorporated the patches contained in p03400.zip for
file rabmch.c to correct for an error in the processing
of the "ret cc" instruction.
12. Made many corrections to internal code comments.
APPENDIX E
CONTRIBUTORS
Contributing Authors:
Marko Makela First Author: AS6500
Marko dot Makela at Helsinki dot Fi
John L. Hartman First Author: AS8051
noice at noicedebugger dot com ASxxxx Internals
G. Osborn Contributed To: LKS19.C and LKIXX.C
gary at s-4 dot com
Ken Hornstein Contributed To: Object Libraries
kenh at cmf dot nrl dot navy dot mil
Bill McKinnon CoAuthor: AS8XCXXX
w_mckinnon at conknet dot com
Roger Ivie First Author: ASGB
ivie at cc dot usu dot edu
Uwe Stellar First Author: AS740
Uwe dot Steller at t-online dot de
Shugen Chen First Author: AS1802
schen at devry dot edu
Edgar Puehringer First Author: AS61860
edgar_pue at yahoo dot com
Ulrich Raich / Razaq Ijoduola First Authors: ASRAB
Ulrich dot Raich at cern dot ch
Patrick Head First Author: ASEZ80
patrick at phead dot net
CONTRIBUTORS Page E-2
Boisy G. Pitre Tandy Color Computer Disk Basic Binary
boisy at boisypitre dot com .ifxx directives
Mike McCarty Processor Cycle Count Option
mike dot mccarty at sbcglobal dot net
Mengjin Su PIC18Fxxx Extended Instructions
msu at micron dot com
Carl Rash Visual Studio 2010 Project Files
crash at triad dot rr dot com
John Coffman First Author: ASZ280
johninsd at gmail dot com
Mike Naberezny Suggestions and Debugging: AS78K0
mike at naberezny dot com
Mike Bezera Extensive Debugging: AS6816
mikebezera at gmail dot com
And thanks to all those who took the time to
send bug reports, suggest changes, or simply
sent a note of encouragement. These were and
are greatly appreciated. Thank you.
APPENDIX F
NOTES AND TIPS
In no particular order are some notes and tips on using the
ASxxxx assemblers that users have asked about.
F.1 REGISTER RENAMING
Sometimes it is convenient to give alternate names to a
processor's registers to improve readability or make your code
more descriptive.
For almost all the assemblers the registers are defined in-
ternally and do not have a value. This means that using an
equate statement will fail:
iptr .equ R3 / iptr = R3
and will give a , undefined, error.
Use the .define directive to specify the alternate name for a
register:
.define keyword ^/string'
e.g.
.define iptr ^/R3/
The assembler, when it finds the key word 'iptr', will first
replace the string 'iptr' with 'R3' and then process the line.
(Note that the the keyword must start with a letter.)
NOTES AND TIPS PAGE F-2
AREAS AND BANKS
F.2 AREAS AND BANKS
The .area and .bank directives are just a means of organiz-
ing, ordering, combining, and placing code where you want it.
An example might be the construction of an area which con-
tains addresses of messages and an area containing the messages.
In this case define an area which will only contain the base ad-
dress of the address table, the second will contain the list of
addresses, and the third which will contain the messages.
.area msgbas ; Message address base
.area msgadr ; Message addresses
.area msgs ; Messages
Then insert message addresses in area msgaddr and messages in
area msgs:
.area msgbas ; Base of msgadr table
msgadr:
.area msgadr
.word msg01 ; Address of message 1
.word msg02 ; Address of message 2
...
.area msgs
msg01: .asciz "Message Number 1"
msg02: .asciz "Message Number 2"
...
.area MyCode ; Reselect Code Area
(Note: be sure to reselect the code area you want before
continueing with your coding.)
At any further point in your source code you can insert addi-
tional messages in the table by simply repeating the process:
NOTES AND TIPS PAGE F-3
AREAS AND BANKS
.area msgadr
.word msg03 ; Address of message 3
...
.area msgs
msg03: .asciz "Message Number 3"
...
.area MyCode ; Reselect Code Area
with the message addresses and messages appended to the previous
entries. (Note that the label msgadr, which is the beginning of
the address table, is required to be presented to the linker be-
fore area msgadr.)
This procedure can be replicated as needed and also in other
assembly files. The ordering will be defined by the order in
which the individually assembled modules are linked. This may
be especially useful when linking optional modules and want
their messages included in the same dispatch table.
It will be easier to manage your areas by creating an assem-
bly file which contains the ordering of your code and including
it in all your assembly files or assemble this definition file
and make it the first file when linking your project.
In this example the definition file should contain the fol-
lowing three areas:
...
.area msgbas ; Message Base
.area msgadr ; Message Addresses
.area msgs ; Messages
...
The bank directive allows the programmer to position code
anywhere in the address space of the processor. Suppose it is
desired to place the message tables at location 0x6000 in the
processor address space. The bank directives might be:
.bank MsgTbl (Base=0x6000)
and the area definitions should be changed to place the code
into the specific bank:
NOTES AND TIPS PAGE F-4
AREAS AND BANKS
...
.area msgbas (Bank=MsgTbl) ; Message Base
.area msgadr (Bank=MsgTbl) ; Message Addresses
.area msgs (Bank=MsgTbl) ; Messages
...
One should note that by using a definition file, which con-
tains all the area/bank options, all other assembly files need
only .area directives with the area name.
F.3 INHIBITING INCLUDE FILE PAGINATION
The default actions when the .include directive is invoked
are:
1) Interrupt current assembly processing
2) Start a New Page
3) Assemble include file statements
4) Start a New Page
5) Continue assembling where interrupted
To inhibit the 'Start a New Page' steps when including a
file, insert the appropriate listing directives as shown in this
example.
.nlist ; Inhibits Pagination
.include "area.def" ; Include the File
.list ; Restart Listing
Because the .nlist directive also applies to the include file
you must place an appropriate .list directive in the include
file. At completion of the include file processing listing au-
tomatically reverts to the .nlist mode and pagination is again
suppressed. The .list directive then restores normal listing as
assembly processing continues.
NOTES AND TIPS PAGE F-5
INHIBITING INCLUDE FILE PAGINATION
NOTE
If the assembled include file generates output object
code and a .rst file is going to be created by the
linker, then the assembler listing file must include
the .list options (loc,bin) for regular code or (meb)
for macro generated code. Failure to include all
generated code in the listing file will result in
translation errors in the .rst file.
When inserting an included file using the above technique and
there is no listing directive within the file, then the result-
ing assembler listing file will show no indication the file was
actually included. .list and .nlist are never shown in the out-
put listing file. To indicate the file was included, using the
example Area/Bank definition file, one might list a single line
description of the inclusion by inserting these lines in the in-
cluded file.
.list (!,src)
; area.def Areas/Banks Defined
.nlist
Then the result of
.nlist ; Inhibits Pagination
.include "area.def" ; Include the File
.list ; Restart Listing
will be a single line in the assembly listing:
; area.def Areas/Banks Defined
F.4 TO INCLUDE OR TO INCLUDE
When building a project there is always the decision to as-
semble multiple files together on the command line, use the .in-
clude directive to insert assembly files into the project, or to
assemble files seperately and then combine them using the
linker.
When coding reusable modules it may be more convenient to as-
semble these modules seperately. However this also requires a
method to define the global entry points and data for the
NOTES AND TIPS PAGE F-6
TO INCLUDE OR TO INCLUDE
calling program. The following technique allows any of the
three methods described to be used.
The module is designed in such a way that it can be used as
an independent module, included module, and a globals definition
file. The first step is to open a file, perhaps 'fnctns.asm',
inhibit listing, and create a macro which holds all the global
definitions:
.nlist
.macro fnctns.globals
.globl func1 ; function 1
.globl func2 ; function 2
.globl inpval ; input variable
.globl outval ; ouput variable
.endm
Next add code that invokes just the globals or the globals
and the module's code. Do this by using a conditional that
checks if a specific label has been defined. As an example use
the string "_fnctns" as the label that must be defined.
.ifdef "_fnctns"
fnctns.globals
.else
.list
fnctns.globals
... ; module code
...
...
.nlist
.endif
This file can be assembled as a seperate module or as an in-
cluded file in the project. If the project is built by linking
this module with other modules then any module which references
the functions or variables in the module "fnctns.asm" will need
these to be defined. Add this code to any module using the mod-
ule "fnctns".
NOTES AND TIPS PAGE F-7
TO INCLUDE OR TO INCLUDE
.define "_fnctns" ; key word
.nlist ; Inhibits Pagination
.include "fnctns.asm" ; Include the File
.list ; Restart Listing
This results in only the globals being defined for the module
"fnctns.asm".
APPENDIX AA
ASCHECK ASSEMBLER
The ASxxxx assembler ASCHECK is used to test the machine in-
dependent features of the ASxxxx assemblers. The source files
for the ASCHECK assembler are also useful as a template for the
development of a new ASxxxx assembler.
The ASCHECK assembler has all the ASxxxx directives enabled
for testing all features of the assemblers.
ASCHECK ASSEMBLER Page AA-2
AA.1 .opcode DIRECTIVE
Format:
.opcode n
The .opcode directive creates a single byte of code having the
value n and having cycle counts defined in the following table:
/*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
/*--*--* - - - - - - - - - - - - - - - - */
/*00*/ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,
/*10*/ UN, 1,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
/*20*/ UN,UN, 2,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
/*30*/ UN,UN,UN, 3,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
/*40*/ UN,UN,UN,UN, 4,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
/*50*/ UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
/*60*/ UN,UN,UN,UN,UN,UN, 6,UN,UN,UN,UN,UN,UN,UN,UN,UN,
/*70*/ UN,UN,UN,UN,UN,UN,UN, 7,UN,UN,UN,UN,UN,UN,UN,UN,
/*80*/ UN,UN,UN,UN,UN,UN,UN,UN, 8,UN,UN,UN,UN,UN,UN,UN,
/*90*/ UN,UN,UN,UN,UN,UN,UN,UN,UN, 9,UN,UN,UN,UN,UN,UN,
/*A0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,10,UN,UN,UN,UN,UN,
/*B0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,11,UN,UN,UN,UN,
/*C0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,12,UN,UN,UN,
/*D0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,13,UN,UN,
/*E0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,14,UN,
/*F0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,15
The UN symbols indicate 'undefined cycles' where no cycle count
will be output.
APPENDIX AB
AS1802 ASSEMBLER
AB.1 ACKNOWLEDGMENT
Thanks to Shujen Chen for his contribution of the AS1802
cross assembler.
Shujen Chen
DeVry University
Tinley Park, IL
schen at tp dot devry dot edu
AB.2 1802 REGISTER SET
The following is a list of the 1802 registers used by AS1802:
r0-r15 - 8-bit registers
sp - register r2
pc - register r3
call - register r4
return - register r5
argr - register r6
AS1802 ASSEMBLER PAGE AB-2
1802 INSTRUCTION SET
AB.3 1802 INSTRUCTION SET
The following tables list all 1802 mnemonics recognized by
the AS1802 assembler. The designation [] refers to a required
addressing mode argument. The following list specifies the
format for each addressing mode supported by AS1802:
#data immediate data
byte or word data
expr expression
Rn register addressing
label branch label
The terms data, expr, and label may be expressions.
Note that not all addressing modes are valid with every in-
struction, refer to the 1802 technical data for valid modes.
AB.3.1 1802 Inherent Instructions
adc add and
dis idl irx
ldx ldxa lsdf
lsie lskp lsnf
lsnq lsnz lsq
lsz mark nop
or req ret
rshl rshr sav
sd sdb seq
shl shlc shr
shrc skp sm
smb stxd xor
AS1802 ASSEMBLER PAGE AB-3
1802 INSTRUCTION SET
AB.3.2 1802 Short Branch Instructions
b1 label b2 label
b3 label b4 label
bdf label bge label
bl label bm label
bn1 label bn2 label
bn3 label bn4 label
bnf label bnq label
bnz label bpz label
bq label br label
bz label nbr label
AB.3.3 1802 Long Branch Instructions
lbdf label lbnf label
lbnq label lbnz label
lbq label lbr label
lbz label nlbr label
AB.3.4 1802 Immediate Instructions
adci #data adi #data
ani #data ldi #data
ori #data sdbi #data
sdi #data smbi #data
smi #data xri #data
AB.3.5 1802 Register Instructions
dec Rn ghi Rn
glo Rn inc Rn
lda Rn ldn Rn
phi Rn plo Rn
sep Rn sex Rn
str Rn
AS1802 ASSEMBLER PAGE AB-4
1802 INSTRUCTION SET
AB.3.6 1802 Input and Output Instructions
inp expr
out expr
AS1802 ASSEMBLER PAGE AB-5
1802 INSTRUCTION SET
AB.3.7 CDP1802 COSMAC Microprocessor Instruction Set Summary
----------------------------------------------------------------
| |
| |
| RCA |
| |
| 1 88888 000 22222 |
| 11 8 8 0 0 2 2 |
| 1 8 8 0 0 0 2 |
| 1 88888 0 0 0 222 |
| 1 8 8 0 0 0 2 |
| 1 8 8 0 0 2 |
| 111 88888 000 2222222 |
| |
| CDP1802 COSMAC Microprocessor Instruction Set Summary |
| |
| |
| |
| |
|Written by Jonathan Bowen |
| Programming Research Group |
| Oxford University Computing Laboratory |
| 8-11 Keble Road |
| Oxford OX1 3QD |
| England |
| |
| Tel +44-865-273840 |
| |
|Created August 1981 |
|Updated April 1985 |
|Issue 1.3 Copyright (C) J.P.Bowen 1985|
----------------------------------------------------------------
AS1802 ASSEMBLER PAGE AB-6
1802 INSTRUCTION SET
----------------------------------------------------------------
| |
| CDP1802 COSMAC Microprocessor Pinout |
| |
| _________ _________ |
| _| \__/ |_ |
| --> CLOCK |_|1 40|_| Vdd |
| ____ _| |_ ____ |
| --> WAIT |_|2 39|_| XTAL --> |
| _____ _| |_ ______ |
| --> CLEAR |_|3 38|_| DMA IN <-- |
| _| |_ _______ |
| <-- Q |_|4 37|_| DMA OUT <-- |
| _| |_ _________ |
| <-- SC1 |_|5 36|_| INTERRUPT <-- |
| _| |_ ___ |
| <-- SC0 |_|6 35|_| MWR <-- |
| ___ _| |_ |
| <-- MRD |_|7 34|_| TPA --> |
| _| |_ |
| <--> BUS 7 |_|8 33|_| TPB --> |
| _| |_ |
| <--> BUS 6 |_|9 32|_| MA7 --> |
| _| |_ |
| <--> BUS 5 |_|10 1802 31|_| MA6 --> |
| _| |_ |
| <--> BUS 4 |_|11 30|_| MA5 --> |
| _| |_ |
| <--> BUS 3 |_|12 29|_| MA4 --> |
| _| |_ |
| <--> BUS 2 |_|13 28|_| MA3 --> |
| _| |_ |
| <--> BUS 1 |_|14 27|_| MA2 --> |
| _| |_ |
| <--> BUS 0 |_|15 26|_| MA1 --> |
| _| |_ |
| Vcc |_|16 25|_| MA0 --> |
| _| |_ ___ |
| <-- N2 |_|17 24|_| EF1 <-- |
| _| |_ ___ |
| <-- N1 |_|18 23|_| EF2 <-- |
| _| |_ ___ |
| <-- N0 |_|19 22|_| EF3 <-- |
| _| |_ ___ |
| Vss |_|20 21|_| EF4 <-- |
| |______________________| |
| |
| |
----------------------------------------------------------------
AS1802 ASSEMBLER PAGE AB-7
1802 INSTRUCTION SET
----------------------------------------------------------------
|Mnem. |Op|F|Description |Notes |
|------+--+-+----------------------------+---------------------|
|ADC |74|*|Add with Carry |{DF,D}=mx+D+DF |
|ADCI i|7C|*|Add with Carry Immediate |{DF,D}=mp+D+DF,p=p+1 |
|ADD |F4|*|Add |{DF,D}=mx+D |
|ADI i|FC|*|Add Immediate |{DF,D}=mp+D,p=p+1 |
|AND |F2|*|Logical AND |D={mx}&D |
|ANI i|FA|*|Logical AND Immediate |D={mp}&D,p=p+1 |
|B1 a|34|-|Branch if EF1 |If EF1=1 BR else NBR |
|B2 a|35|-|Branch if EF2 |If EF2=1 BR else NBR |
|B3 a|36|-|Branch if EF3 |If EF3=1 BR else NBR |
|B4 a|37|-|Branch if EF4 |If EF4=1 BR else NBR |
|BDF a|33|-|Branch if DF |If DF=1 BR else NBR |
|BGE a|33|-|Branch if Greater or Equal |See BDF |
|BL a|38|-|Branch if Less |See BNF BR else NBR |
|BM a|38|-|Branch if Minus |See BNF |
|BN1 a|3C|-|Branch if Not EF1 |If EF1=0 BR else NBR |
|BN2 a|3D|-|Branch if Not EF2 |If EF2=0 BR else NBR |
|BN3 a|3E|-|Branch if Not EF3 |If EF3=0 BR else NBR |
|BN4 a|3F|-|Branch if Not EF4 |If EF4=0 BR else NBR |
|BNF a|38|-|Branch if Not DF |If DF=0 BR else NBR |
|BNQ a|39|-|Branch if Not Q |If Q=0 BR else NBR |
|BNZ a|3A|-|Branch if D Not Zero |If D=1 BR else NBR |
|BPZ a|33|-|Branch if Positive or Zero |See BDF |
|BQ a|31|-|Branch if Q |If Q=1 BR else NBR |
|BR a|30|-|Branch |pl=mp |
|BZ a|32|-|Branch if D Zero |If D=0 BR else NBR |
|DEC r|2N|-|Decrement register N |n=n-1 |
|DIS |71|-|Disable |{X,P}=mx,x=x+1,IE=0 |
|GHI r|9N|-|Get High register N |D=nh |
|GLO r|8N|-|Get Low register N |D=nl |
|IDL |00|-|Idle (wait for DMA or int.) |Bus=m0 |
|INC r|1N|-|Increment register N |n=n+1 |
|INP d|6N|-|Input (N=d+8=9-F) |mx=Bus,D=Bus,Nlines=d|
|IRX |60|-|Increment register X |x=x+1 |
|LBDF a|C3|-|Long Branch if DF |If DF=1 LBR else LNBR|
|LBNF a|C8|-|Long Branch if Not DF |If DF=0 LBR else LNBR|
|LBNQ a|C9|-|Long Branch if Not Q |If Q=0 LBR else LNBR |
|LBNZ a|CA|-|Long Branch if D Not Zero |If D=1 LBR else LNBR |
----------------------------------------------------------------
AS1802 ASSEMBLER PAGE AB-8
1802 INSTRUCTION SET
----------------------------------------------------------------
|Mnem. |Op|F|Description |Notes |
|------+--+-+----------------------------+---------------------|
|LBQ a|C1|-|Long Branch if Q |If Q=1 LBR else LNBR |
|LBR a|C0|-|Long Branch |p=mp |
|LBZ a|C2|-|Long Branch if D Zero |If D=0 LBR else LNBR |
|LDA r|4N|-|Load advance |D=mn,n=n+1 |
|LDI i|F8|-|Load Immediate |D=mp,p=p+1 |
|LDN r|0N|-|Load via N (except N=0) |D=mn |
|LDX |F0|-|Load via X |D=mx |
|LDXA |72|-|Load via X and Advance |D=mx,x=x+1 |
|LSDF |CF|-|Long Skip if DF |If DF=1 LSKP else NOP|
|LSIE |CC|-|Long Skip if IE |If IE=1 LSKP else NOP|
|LSKP |C8|-|Long Skip |See NLBR |
|LSNF |C7|-|Long Skip if Not DF |If DF=0 LSKP else NOP|
|LSNQ |C5|-|Long Skip if Not Q |If Q=0 LSKP else NOP |
|LSNZ |C6|-|Long Skip if D Not Zero |If D=1 LSKP else NOP |
|LSQ |CD|-|Long Skip if Q |If Q=1 LSKP else NOP |
|LSZ |CE|-|Long Skip if D Zero |If D=0 LSKP else NOP |
|MARK |79|-|Push X,P to stack (T={X,P})|m2={X,P},X=P,r2=r2-1 |
|NBR |38|-|No short Branch (see SKP) |p=p+1 |
|NLBR a|C8|-|No Long Branch (see LSKP) |p=p+2 |
|NOP |C4|-|No Operation |Continue |
|OR |F1|*|Logical OR |D={mx}vD |
|ORI i|F9|*|Logical OR Immediate |D={mp}vD,p=p+1 |
|OUT d|6N|-|Output (N=d=1-7) |Bus=mx,x=x+1,Nlines=d|
|PLO r|AN|-|Put Low register N |nl=D |
|PHI r|BN|-|Put High register N |nh=D |
|REQ |7A|-|Reset Q |Q=0 |
|RET |70|-|Return |{X,P}=mx,x=x+1,IE=1 |
|RSHL |7E|*|Ring Shift Left |See SHLC |
|RSHR |76|*|Ring Shift Right |See SHRC |
----------------------------------------------------------------
AS1802 ASSEMBLER PAGE AB-9
1802 INSTRUCTION SET
----------------------------------------------------------------
|Mnem. |Op|F|Description |Notes |
|------+--+-+----------------------------+---------------------|
|SAV |78|-|Save |mx=T |
|SDB |75|*|Subtract D with Borrow |{DF,D}=mx-D-DF |
|SDBI i|7D|*|Subtract D with Borrow Imm. |{DF,D}=mp-D-DF,p=p+1 |
|SD |F5|*|Subtract D |{DF,D}=mx-D |
|SDI i|FD|*|Subtract D Immediate |{DF,D}=mp-D,p=p+1 |
|SEP r|DN|-|Set P |P=N |
|SEQ |7B|-|Set Q |Q=1 |
|SEX r|EN|-|Set X |X=N |
|SHL |FE|*|Shift Left |{DF,D}={DF,D,0}<- |
|SHLC |7E|*|Shift Left with Carry |{DF,D}={DF,D}<- |
|SHR |F6|*|Shift Right |{D,DF}=->{0,D,DF} |
|SHRC |76|*|Shift Right with Carry |{D,DF}=->{D,DF} |
|SKP |38|-|Short Skip |See NBR |
|SMB |77|*|Subtract Memory with Borrow |{DF,D}=D-mx-{~DF} |
|SMBI i|7F|*|Subtract Mem with Borrow Imm|{DF,D}=D-mp-~DF,p=p+1|
|SM |F7|*|Subtract Memory |{DF,D}=D-mx |
|SMI i|FF|*|Subtract Memory Immediate |{DF,D}=D-mp,p=p+1 |
|STR r|5N|-|Store via N |mn=D |
|STXD |73|-|Store via X and Decrement |mx=D,x=x-1 |
|XOR |F3|*|Logical Exclusive OR |D={mx}.D |
|XRI i|FB|*|Logical Exclusive OR Imm. |D={mp}.D,p=p+1 |
| | |-|Interrupt action |T={X,P},P=1,X=2,IE=0 |
|------+--+-+--------------------------------------------------|
| |??| |8-bit hexadecimal opcode |
| |?N| |Opcode with register/device in low 4/3 bits |
| | |-|DF flag unaffected |
| | |*|DF flag affected |
----------------------------------------------------------------
AS1802 ASSEMBLER PAGE AB-10
1802 INSTRUCTION SET
----------------------------------------------------------------
|Arguments | Notes |
|-----------+--------------------------------------------------|
| mn |Register addressing |
| mx |Register-indirect addressing |
| mp |Immediate addressing |
| R( ) |Stack addressing (implied addressing) |
|-----------+--------------------------------------------------|
| D |Data register (accumulator, 8-bit) |
| DF |Data Flag (ALU carry, 1-bit) |
| I |High-order instruction digit (4-bit) |
| IE |Interrupt Enable (1-bit) |
| N |Low-order instruction digit (4-bit) |
| P |Designates Program Counter register (4-bit) |
| Q |Output flip-flop (1-bit) |
| R |1 of 16 scratchpad Registers(16-bit) |
| T |Holds old {X,P} after interrupt (X high, 8-bit) |
| X |Designates Data Pointer register (4-bit) |
|-----------+--------------------------------------------------|
| mn |Memory byte addressed by R(N) |
| mp |Memory byte addressed by R(P) |
| mx |Memory byte addressed by R(X) |
| m? |Memory byte addressed by R(?) |
| n |Short form for R(N) |
| nh |High-order byte of R(N) |
| nl |Low-order byte of R(N) |
| p |Short form for R(P) |
| pl |Low-order byte of R(P) |
| r? |Short form for R(?) |
| x |Short form for R(X) |
|-----------+--------------------------------------------------|
| R(N) |Register specified by N |
| R(P) |Current program counter |
| R(X) |Current data pointer |
| R(?) |Specific register |
----------------------------------------------------------------
AS1802 ASSEMBLER PAGE AB-11
1802 INSTRUCTION SET
----------------------------------------------------------------
|Arguments | Notes |
|-----------+--------------------------------------------------|
| a |Address expression |
| d |Device number (1-7) |
| i |Immediate expression |
| n |Expression |
| r |Register (hex digit or an R followed by hex digit)|
|-----------+--------------------------------------------------|
| + |Arithmetic addition |
| - |Arithmetic subtraction |
| * |Arithmetic multiplication |
| / |Arithmetic division |
| & |Logical AND |
| ~ |Logical NOT |
| v |Logical inclusive OR |
| . |Logical exclusive OR |
| <- |Rotate left |
| -> |Rotate right |
| { } |Combination of operands |
| ? |Hexadecimal digit (0-F) |
| --> |Input pin |
| <-- |Output pin |
| <--> |Input/output pin |
----------------------------------------------------------------
APPENDIX AC
AS2650 ASSEMBLER
AC.1 2650 REGISTER SET
The following is a list of the 2650 registers used by AS2650:
r0,r1 - 8-bit accumulators
r2,r3
AC.2 2650 INSTRUCTION SET
The following tables list all 2650 mnemonics recognized by
the AS2650 assembler. The designation [] refers to a required
addressing mode argument. The designation CC refers to a re-
quired condition code argument: .eq., .gt., .lt., .un., or
value of 0-3. The following list specifies the format for each
addressing mode supported by AS2650:
#data immediate byte data
r0,r1,r2,r3 registers
addr location/branch address
[addr] or indirect addressing
@addr
[addr,r0] or register indexed
@addr,r0 indirect addressing
[addr,-r0] or autodecrement register indexed
@addr,-r0 indirect addressing
AS2650 ASSEMBLER PAGE AC-2
2650 INSTRUCTION SET
[addr,r0+] or autoincrement register indexed
@addr,r0+ indirect addressing
.eq. CC: equal (== 0)
.gt. CC: greater than (== 1)
.lt. CC: less than (== 2)
.un. CC: unconditional (== 3)
The terms data, label, and addr may all be expressions.
Note that not all addressing modes are valid with every in-
struction, refer to the 2650 technical data for valid modes.
AC.2.1 Load / Store Instructions
lodz r lodi #data
lodr [] loda []
stoz r
stor [] stoa []
AC.2.2 Arithmetic / Compare Instructions
addz r addi #data
addr [] adda []
subz r subi #data
subr [] suba []
comz r comi #data
comr [] coma []
dar r
AC.2.3 Logical / Rotate Instructions
andz r andi #data
andr [] anda []
iorz r iori #data
iorr [] iora []
eorz r eori #data
eorr [] eora []
rrr r
AS2650 ASSEMBLER PAGE AC-3
2650 INSTRUCTION SET
rrl r
AC.2.4 Condition Code Branches
bctr CC,[] bcta CC,[]
bcfr CC,[] bcfa CC,[]
bstr CC,[] bsta CC,[]
bsfr CC,[] bsta CC,[]
AC.2.5 Register Test Branches
brnr r,[] brna r,[]
birr r,[] bira r,[]
bdrr r,[] bdra r,[]
bsnr r,[] bsna r,[]
AC.2.6 Branches (to Subroutines) / Returns
bxa [] bsxa []
zbrr [] zbsr []
retc CC rete CC
AC.2.7 Input / Output
redc r wrtc r
redd r wrtd r
rede r,addr wrte r,addr
AS2650 ASSEMBLER PAGE AC-4
2650 INSTRUCTION SET
AC.2.8 Miscellaneos
halt nop
tmi r,#data
AC.2.9 Program Status
lpsl lpsu
spsl spsu
cpsl #data cpsu #data
ppsl #data ppsu #data
tpsl #data tpsu #data
APPENDIX AD
AS430 ASSEMBLER
AD.1 MPS430 REGISTER SET
The following is a list of the MPS430 registers used by AS430:
Sixteen 16-bit registers provide adddress, data, and
special functions:
pc / r0 - program counter
sp / r1 - stack pointer
sr / r2 - status register
cg1 / r2 - constant generator 1
cg2 / r3 - constant generator 2
r4 - working register r4
r5 - working register r5
...
r14 - working register r14
r15 - working register r15
AS430 ASSEMBLER PAGE AD-2
MPS430 REGISTER SET
AD.2 MPS430 ADDRESSING MODES
The following list specifies the format for each addressing
mode supported by AS430:
Source/Destination Operand Addressing Modes
As/Ad Addressing Mode Syntax Description
----- --------------- ------ -----------
00/0 Register mode Rn Register contents are operand.
01/1 Indexed mode X(Rn) (Rn + X) points to the operand,
X is stored in the next word.
01/1 Symbolic mode ADDR (PC + X) points to the operand,
X is stored in the next word,
Indexed mode X(PC) is used.
01/1 Absolute mode &ADDR The word following the
instruction, contains the
absolute address.
10/- Indirect @Rn Rn is used as a pointer to the
register mode operand.
11/- Indirect @Rn+ Rn is used as a pointer to the
autoincrement operand. Rn is incremented
afterwards.
11/- Immediate mode #N The word following the
instruction contains the
immediate constant N. Indirect
autoincrement mode @PC+ is used.
The terms ADDR, X and N may all be expressions.
Note that not all addressing modes are valid with every in-
struction, refer to the MPS430 technical data for valid modes.
AS430 ASSEMBLER PAGE AD-3
MPS430 ADDRESSING MODES
AD.2.1 MPS430 Instruction Mnemonics
The following table lists all MPS430 family mnemonics recognized
by the AS430 assembler. The designations src and dst refer to
required source and/or destination addressing mode arguments.
* ADC[.W];ADC.B dst dst + C -> dst
ADD[.W];ADD.B src,dst src + dst -> dst
ADDC[.W];ADDC.B src,dst src + dst + C -> dst
AND[.W];AND.B src,dst src .and. dst -> dst
BIC[.W];BIC.B src,dst .not.src .and. dst -> dst
BIS[.W];BIS.B src,dst src .or. dst -> dst
BIT[.W];BIT.B src,dst src .and. dst
* BR dst Branch to .......
* BRANCH dst Branch to .......
CALL dst PC+2 -> stack, dst -> PC
* CLR[.W];CLR.B dst Clear destination
* CLRC Clear carry bit
* CLRN Clear negative bit
* CLRZ Clear zero bit
CMP[.W];CMP.B src,dst dst - src
* DADC[.W];DADC.B dst dst + C -> dst (decimal)
DADD[.W];DADD.B src,dst src + dst + C -> dst (decimal)
* DEC[.W];DEC.B dst dst - 1 -> dst
* DECD[.W];DECD.B dst dst - 2 -> dst
* DINT Disable interrupt
* EINT Enable interrupt
* INC[.W];INC.B dst dst + 1 -> dst
* INCD[.W];INCD.B dst dst + 2 -> dst
* INV[.W];INV.B dst Invert destination
JC/JHS Label Jump to Label if Carry-bit is set
JEQ/JZ Label Jump to Label if Zero-bit is set
JGE Label Jump to Label if (N .XOR. V) = 0
JL Label Jump to Label if (N .XOR. V) = 1
JMP Label Jump to Label unconditionally
JN Label Jump to Label if Negative-bit is set
JNC/JLO Label Jump to Label if Carry-bit is reset
JNE/JNZ Label Jump to Label if Zero-bit is reset
MOV[.W];MOV.B src,dst src -> dst
* NOP No operation
AS430 ASSEMBLER PAGE AD-4
MPS430 ADDRESSING MODES
* POP[.W];POP.B dst Item from stack, SP+2 -> SP
PUSH[.W];PUSH.B src SP - 2 -> SP, src -> @SP
RETI Return from interrupt
TOS -> SR, SP + 2 -> SP
TOS -> PC, SP + 2 -> SZP
* RET Return from subroutine
TOS -> PC, SP + 2 -> SP
* RLA[.W];RLA.B dst Rotate left arithmetically
* RLC[.W];RLC.B dst Rotate left through carry
RRA[.W];RRA.B dst MSB -> MSB . ....LSB -> C
RRC[.W];RRC.B dst C -> MSB . ......LSB -> C
* SBC[.W];SBC.B dst Subtract carry from destination
* SETC Set carry bit
* SETN Set negative bit
* SETZ Set zero bit
SUB[.W];SUB.B src,dst dst + .not.src + 1 -> dst
SUBC[.W];SUBC.B src,dst dst + .not.src + C -> dst
SBB[.W];SBB.B src,dst dst + .not.src + C -> dst
SWPB dst swap bytes
SXT dst Bit7 -> Bit8 ........ Bit15
* TST[.W];TST.B dst Test destination
XOR[.W];XOR.B src,dst src .xor. dst -> dst
Note: Asterisked Instructions
Asterisked (*) instructions are emulated.
They are replaced with coreinstructions
by the assembler.
APPENDIX AE
AS6100 ASSEMBLER
AE.1 6100 MACHINE DESCRIPTION
The IM6100 (Intersil) and HM6100 (Harris) microprocessors are
12-bit word addressable machines having three 12-bit program ac-
cessible registers and one single bit register. These are the
Accumulator (AC), MQ Register (MQ), Program Counter (PC), and
the Link (L) respectively.
The 6100 is basically a clone of the Digital Equipment Cor-
poration PDP-8E minicomputer architecture. This architecture
predates all microprocessors and labeled the bits from 0 (the
most significant) to 11 (the least significant) rather than from
least to most significant. The actual labelling is arbitrary
and the as6100 assembler uses the now more common labelling.
The output generated from the assembler/linker is two bytes
per word ordered as MSB then LSB with the upper 4 bits of the
MSB always zero.
AE.2 ASSEMBLER SPECIFIC DIRECTIVES
Because the 6100 microprocessor has no concept of bytes
several of the cross assembler directives have their operation
changed to reflect the 12-Bit nature of the microprocessor.
These are:
.byte (.db and .fcb are aliases)
output an 8-Bit value
into a 12-bit word
.word (.dw and .fdb are aliases)
AS6100 ASSEMBLER PAGE AE-2
ASSEMBLER SPECIFIC DIRECTIVES
output a 12-Bit value
into a 12-Bit word
.ascii (.asciz and ascis also)
output a sequence of 8-Bit
characters in 12-bit words
A double precision integer (24-Bits) mnemonic has been added:
.dubl (.4byte and .quad are aliases)
output a 24-Bit value
into two 12-bit words
Two new directives have been added to implement 6-bit
character string operations. The characters A-Z and [/]^_ are
masked to values of 0x01 to 0x1F, the characters a-z are masked
to values of 0x01 to 0x1A, and the characters from ' ' (space)
to '?' are masked to 0x20 to 0x3F. All other ascii characters
become a space (0x20).
These are:
.text output upto two characters per 12-bit
word
.textz output upto two characters per 12-bit
word
followed by a 6-bit zero value.
AE.3 MACHINE SPECIFIC DIRECTIVES
The 6100 microprocessor memory architecture consists of 32
pages each having 128 words for a total of 4096 addressable
words. The 6100 instruction set allows direct access only to
the current page and to page 0. Three machine specific direc-
tives provide differing methods to select the memory page.
These directives are:
AS6100 ASSEMBLER PAGE AE-3
MACHINE SPECIFIC DIRECTIVES
AE.3.1 .setpg
Format:
.setpg ; . = next page boundary
.setpg N ; . = Nth page boundary
where: N is the page number from 0 to 31
The .setpg directive is used to set the current program loca-
tion counter to a specific 128 word page boundary or to the next
128 word page boundary and inform the assembler/linker of this
boundary.
AE.3.2 .mempn
Format:
.mempn N ; . = Nth page boundary
where: N is the page number from 0 to 31
The .mempn directive is used to set the current program loca-
tion counter to a specific 128 word page boundary and inform the
assembler/linker of this boundary.
AE.3.3 .mempa
Format:
.mempa A ; . = A (a page boundary)
where: A is a 128 word page address boundary
The .mempa directive is used to set the current program loca-
tion counter to a specific page boundary address and inform the
assembler/linker of this boundary.
AS6100 ASSEMBLER PAGE AE-4
6100 INSTRUCTION SET
AE.4 6100 INSTRUCTION SET
The following tables list all 6100 family mnemonics recog-
nized by the AS6100 assembler. The instruction set is described
in 3 major groupings: Basic Instructions, Operate Microinstruc-
tions, and IOT Instructions.
AE.4.1 Basic Instructions
The basic instructions are:
and Logical AND
tad Binary ADD
isz Increment and skip if zero
dca Deposit and clear AC
jms Jump to subroutine
jmp Jump
These instructions have two paging addressing modes:
addr current page address
*addr page 0 address
which can be combined with an indirect mode signified by an i
argument or enclosing brackets []:
i addr indirect current page
[addr]
i *addr indirect page 0
[*addr] or *[addr]
The 6100 implements an auto-increment mode when accessing ad-
dresses 0x08 - 0x0F in page 0 by incrementing the contents of
the location before using the value as an address.
AS6100 ASSEMBLER PAGE AE-5
6100 INSTRUCTION SET
AE.4.2 Operate Instructions
The operate instructions are split into three groups of mu-
tually exclusive micro operations. The single micro operation
in common with all three groups is:
CLA Clear Accumulator
AE.4.2.1 Group 1 Operate Instructions -
The group 1 microinstructions are used primarily to perform
logical operations on the contents of the accumulator and link:
CLL Clear Link
CMA Complement Accumulator
CML Complement Link
IAC Increment Accumulator
RAL Rotate Accumulator Left
RTL Rotate Two Left
RAR Rotate Accumulator Right
RTR Rotate Two Right
BSW Byte Swap
A group 1 microinstruction can contain one or all of the mnemon-
ics CLA, CLL, CMA, CML, IAC, but only one of the RAL, RTL, RAR,
RTR, or BSW mnemonics (RAL, RTL, RAR, RTR, and BSW are mutually
exclusive).
The NOP (No Operation) functionality can be implemented in
all three operate instruction groups but is specified by the as-
sembler as a group 1 instruction.
Several common group 1 operations have been given their own
mnemonics:
NOP NO Operation
CIA Complement and Increment Accumulator
GLT Get Link
STA Set Accumulator
AS6100 ASSEMBLER PAGE AE-6
6100 INSTRUCTION SET
AE.4.2.2 Group 2 Operate Instructions -
The group 2 microinstructions are used primarily to test the
contents of the accumulator and/or link and then conditionally
skip the next sequential instruction:
HLT Halt
OSR Or With Switch Register
SKP Skip
SNL Skip On Non-Zero Link
SZL Skip On Zero Link
SZA Skip On Zero Accumulator
SNA Skip On Non-Zero Accumulator
SMA Skip On Minus Accumulator
SPA Skip On Plus Accumulator
A group 2 microinstruction can contain one or all of the mnemon-
ics CLA, HLT, OSR, but only one of the SKP, SNL, SZL, SZA, SNA,
SMA, or SPA mnemonics (SKP, SNL, SZL, SZA, SNA, SMA, and SPA are
mutually exclusive).
One common group 2 operation has been given its own mnemonic:
LAS Load Accumulator With Switch Register
AE.4.2.3 Group 3 Operate Instructions -
The group 3 microinstructions perform logical operations on
the contents of AC and MQ.
MQL MQ Register Load
MQA MQ Register Into Accumulator
A group 3 microinstruction can contain one or all of the mnemon-
ics CLA, MQL, and MQA.
Several common group 3 operations have been given their own
mnemonics:
SWP Swap Accumulator and MQ Register
CAM Clear Accumulator and MQ Register
ACL Clear Accumulator and Load
MQ Register into Accumulator
AS6100 ASSEMBLER PAGE AE-7
6100 INSTRUCTION SET
AE.4.2.4 Group Errors -
The 6100 assembler has three additional error codes which oc-
cur when the group 1, 2, or 3 operations are mixed. The error
code will be <1>, <2>, or <3> based upon the first group type
encountered followed by any other type of group operation. The
CLA operation is valid with all groups and does not cause an er-
ror code to be generated.
AE.4.3 Input/Output (IOT) Instructions
The input/output transfer instructions are used to control
the operation of peripherals and transfer data between peri-
pherals and the 6100 microprocessor. Of the lower 9 bits of the
instruction used for device selection and control typically the
3 LSBs are the I/O operation bits and the remaining 6 bits
select the peripheral device.
IOT DEV,CMND
where DEV is the device select code and
CMND is the command code.
Specifying a device select code of zero in the IOT instruction
allows the user program to control the interrupt mechanism of
the 6100 microprocessor. These instructions are:
SKON Skip If Interrupt On
ION Interrupt Turn On
IOF Interrupt Turn Off
SRQ Skip If Int Request
GTF GetFlags
RTF Return Flags
SGT Defined By Device Logic
CAF Clear All Flags
APPENDIX AF
AS61860 ASSEMBLER
AF.1 ACKNOWLEDGMENT
Thanks to Edgar Puehringer for his contribution of the
AS61860 cross assembler.
Edgar Peuhringer
edgar_pue at yahoo dot com
AF.2 61860 REGISTER SET
The SC61860 from Sharp has 96 bytes of internal RAM which are
used as registers and hardware stack. The last four bytes of
the internal RAM are special purpose registers (I/O, timers
...). Here is a list of the 61860 registers:
Reg Address Common use
--- ------- ----------
i, j 0, 1 Length of block operations
a, b 2, 3 Accumulator
xl, xh 4, 5 Pointer for read operations
yl, yh 6, 7 Pointer for write operations
k - n 8 - 0x0b General purpose (counters ...)
- 0x0c - 0x5b Stack
ia 0x5c Inport A
ib 0x5d Inport B
fo 0x5e Outport F
cout 0x5f Control port
Other parts of the 61860 are the 16 bit program counter (pc)
and 16 bit data pointer (dp). The ALU has a carry flag (c) and
AS61860 ASSEMBLER PAGE AF-2
61860 REGISTER SET
a zero flag (z). There is an internal register d which can't be
accessed with machine instructions. It is filled from i or j
when executing block operations.
In addition there are three 7 bit registers p, q, and r which
are used to address the internal RAM (r is the stack pointer, p
and q are used for block operations).
AF.3 PROCESSOR SPECIFIC DIRECTIVES
The AS61860 cross assembler has two (2) processor specific
assembler directives which are used for the etc mnemonic (which
is a kind of a built-in switch/case statement):
.default A 16 bit address (same as .dw)
.case One byte followed by a 16 bit address
Here is an example how this should be used (cut from a lst
file)::
022B 7A 05 02 18 614 PTC 0x05, CONT16
022F 69 615 DTC
0230 4C 01 25 616 .CASE 0x4C, SLOADI
0233 4D 01 2F 617 .CASE 0x4D, SMERGI
0236 51 01 D2 618 .CASE 0x51, QUITI
0239 53 00 CD 619 .CASE 0x53, LLISTI
023C 56 01 D5 620 .CASE 0x56, VERI
023F 01 D1 621 .DEFAULT CONT9
AF.4 61860 INSTRUCTION SET
The following tables list all 61860 family mnemonics recog-
nized by the AS61860 assembler. Most of the mnemonics are con-
verted into 8 bit machine instructions with no argument or a
one- or two-byte argument. There are some exceptions for this:
Mnemonic Description
-------- -----------
jp 2 bit instruction, 6 bit argument
cal 3 bit instruction, 13 bit argument
ptc *) 1 byte instruction, 3 byte argument
dtc *) 1 byte instruction, n bytes argument
*) Not mentioned in the CPU specification from Sharp
AS61860 ASSEMBLER PAGE AF-3
61860 INSTRUCTION SET
AF.4.1 Load Immediate Register
LII n (n --> I)
LIJ n
LIA n
LIB n
LIP n
LIQ n
LIDP nm
LIDL n (DL is the low byte of DP)
LP (One byte version of LIP)
RA (Same as LIA 0, but only one byte)
CLRA (synonym for RA)
AF.4.2 Load Accumulator
LDP (P --> A)
LDQ
LDR
LDM ((P) --> A)
LDD ((DP) --> A)
AF.4.3 Store Accumulator
STP (A --> P)
STQ
STR
STD (A --> (DP))
AF.4.4 Move Data
MVDM ((P) --> (DP))
MVMD ((DP) --> (P))
AS61860 ASSEMBLER PAGE AF-4
61860 INSTRUCTION SET
AF.4.5 Exchange Data
EXAB (A <--> B)
EXAM (A <--> (P))
AF.4.6 Stack Operations
PUSH (R - 1 --> R, A --> (R))
POP ((R) --> A, R + 1 --> R)
LEAVE (0 --> (R))
AF.4.7 Block Move Data
MVW ((Q) --> (P), I+1 bytes)
MVB ((Q) --> (P), J+1 bytes)
MVWD ((DP) --> (P), I+1 bytes)
MVBD ((DP) --> (P), J+1 bytes)
DATA ((B,A) --> (P), I+1 bytes,
reads CPU ROM also)
AF.4.8 Block Exchange Data
EXW ((Q) <--> (P), I+1 bytes)
EXB ((Q) <--> (P), J+1 bytes)
EXWD ((DP) <--> (P), I+1 bytes)
EXBD ((DP) <--> (P), J+1 bytes)
AS61860 ASSEMBLER PAGE AF-5
61860 INSTRUCTION SET
AF.4.9 Increment and Decrement
INCP (P + 1 --> P)
DECP
INCI
DECI
INCJ
DECJ
INCA
DECA
INCB
DECB
INCK
DECK
INCL
DECL
IX (X + 1 --> X, X --> DP)
DX
IY
DY
INCM *)
DECM *)
INCN *)
DECN *)
*) Not mentioned in the CPU specification from Sharp
AF.4.10 Increment/Decrement with Load/Store
IXL (Same as IX plus LDD)
DXL
IYS (Same as IY plus STD)
DYS
AS61860 ASSEMBLER PAGE AF-6
61860 INSTRUCTION SET
AF.4.11 Fill
FILM (A --> (P), I+1 bytes)
FILD (A --> (DP), I+1 bytes)
AF.4.12 Addition and Subtraction
ADIA n (A + n --> A)
SBIA n
ADIM n ((P) + n --> (P))
SBIM n
ADM n ((P) + A --> (P))
SBM n
ADCM n ((P) + A --> (P), with carry)
SBCM
ADB (like ADM, but 16 bit)
SBB
ADN (like ADM, BCD addition, I+1 bytes)
SBN
ADW ((P) + (Q) --> (P), BCD, I+1 bytes)
SBW
AF.4.13 Shift Operations
SRW (shift I+1 bytes in (P) 4 bits right)
SLW
SR (shift A 1 bit, with carry)
SL
SWP (exchange low and high nibble of A)
AF.4.14 Boolean Operations
ANIA n (A & n --> A)
ORIA n
ANIM n ((P) & n --> (P))
ORIM n
ANID n ((DP) & n --> (DP))
ORID n
ANMA ((P) & A --> (P))
ORMA
AS61860 ASSEMBLER PAGE AF-7
61860 INSTRUCTION SET
AF.4.15 Compare
CPIA n (A - n --> c,z)
CPIM n ((P) - n --> c,z)
CPMA ((P) - A --> c,z)
TSIA n (A & n --> z)
TSIM n ((P) & n --> z)
TSID n ((DP) & n --> z)
TSIP ((P) & A --> z)
AF.4.16 CPU Control
SC (Set carry)
RC
NOPW (no op)
NOPT
WAIT n (wait 6+n cycles)
WAITJ (wait 5+4*I cycles)
CUP (synonym for WAITJ)
AF.4.17 Absolute Jumps
JP nm
JPZ nm (on zero)
JPNZ nm
JPC nm
JPNC nm
PTC/DTC (see 'Processor Specific Directives')
PTJ/DTJ (synonym for PTD/DTC)
CPCAL/DTLRA (synonym for PTC/DTC)
CASE1/CASE2 (synonym for PTC/DTC)
SETT/JST (synonym for PTC/DTC)
AS61860 ASSEMBLER PAGE AF-8
61860 INSTRUCTION SET
AF.4.18 Relative Jumps
These operations handle a jump relative to PC forward and
back with a maximum distance of 255 byte. The assembler
resolves 16 bit addresses to to 8 bit relative adresses. If the
target address is to far away, an error will be generated. Note
that relative jumps need 1 byte less than absolute jumps.
JRP nm
JRZP nm
JRNZP nm (jump relative non zero plus direction)
JRCP nm
JRNCP nm
JRM nm
JRZM nm
JRNZM nm
JRCM nm (jump relative on carry minus direction)
JRNCM nm
LOOP nm (decrements (R) and makes a JRNCM)
AF.4.19 Calls
CALL nm
CAL nm (nm must be <= 0x1fff,
1 byte less code than CALL)
RTN
AF.4.20 Input and output
INA (IA --> A)
INB
OUTA
OUTB
OUTF (A --> FO)
OUTC (control port)
TEST n (timers, pins & n --> z)
AS61860 ASSEMBLER PAGE AF-9
61860 INSTRUCTION SET
AF.4.21 Unknown Commands
READ ((PC+1) -> A)
READM ((PC+1) -> (P))
WRIT (???)
APPENDIX AG
AS6500 ASSEMBLER
AG.1 ACKNOWLEDGMENT
Thanks to Marko Makela for his contribution of the AS6500
cross assembler.
Marko Makela
Sillitie 10 A
01480 Vantaa
Finland
Internet: Marko dot Makela at Helsinki dot Fi
EARN/BitNet: msmakela at finuh
Several additions and modifications were made to his code to
support the following families of 6500 processors:
(1) 650X and 651X processor family
(2) 65F11 and 65F12 processor family
(3) 65C00/21 and 65C29 processor family
(4) 65C02, 65C102, and 65C112 processor family
The instruction syntax of this cross assembler contains two
peculiarities: (1) the addressing indirection is denoted by the
square brackets [] and (2) the `bbrx' and `bbsx' instructions
are written `bbr0 memory,label'.
AS6500 ASSEMBLER PAGE AG-2
6500 REGISTER SET
AG.2 6500 REGISTER SET
The following is a list of the 6500 registers used by AS6500:
a - 8-bit accumulator
x,y - index registers
AG.3 6500 INSTRUCTION SET
The following tables list all 6500 family mnemonics recog-
nized by the AS6500 assembler. The designation [] refers to a
required addressing mode argument. The following list specifies
the format for each addressing mode supported by AS6500:
#data immediate data
byte or word data
*dir direct page addressing
(see .setdp directive)
0 <= dir <= 255
offset,x indexed addressing
offset,y indexed addressing
address = (offset + (x or y))
[offset,x] pre-indexed indirect addressing
0 <= offset <= 255
address = contents of location
(offset + (x or y)) mod 256
[offset],y post-indexed indirect addressing
address = contents of location at offset
plus the value of the y register
[address] indirect addressing
ext extended addressing
label branch label
address,label direct page memory location
branch label
bbrx and bbsx instruction addressing
The terms data, dir, offset, address, ext, and label may all be
expressions.
AS6500 ASSEMBLER PAGE AG-3
6500 INSTRUCTION SET
Note that not all addressing modes are valid with every in-
struction, refer to the 65xx technical data for valid modes.
AG.3.1 Processor Specific Directives
The AS6500 cross assembler has four (4) processor specific
assembler directives which define the target 65xx processor
family:
.r6500 Core 650X and 651X family (default)
.r65f11 Core plus 65F11 and 65F12
.r65c00 Core plus 65C00/21 and 65C29
.r65c02 Core plus 65C02, 65C102, and 65C112
AG.3.2 65xx Core Inherent Instructions
brk clc
cld cli
clv dex
dey inx
iny nop
pha php
pla plp
rti rts
sec sed
sei tax
tay tsx
txa txs
tya
AG.3.3 65xx Core Branch Instructions
bcc label bhs label
bcs label blo label
beq label bmi label
bne label bpl label
bvc label bvs label
AS6500 ASSEMBLER PAGE AG-4
6500 INSTRUCTION SET
AG.3.4 65xx Core Single Operand Instructions
asl []
dec []
inc []
lsr []
rol []
ror []
AG.3.5 65xx Core Double Operand Instructions
adc []
and []
bit []
cmp []
eor []
lda []
ora []
sbc []
sta []
AG.3.6 65xx Core Jump and Jump to Subroutine Instructions
jmp [] jsr []
AG.3.7 65xx Core Miscellaneous X and Y Register Instructions
cpx []
cpy []
ldx []
stx []
ldy []
sty []
AS6500 ASSEMBLER PAGE AG-5
6500 INSTRUCTION SET
AG.3.8 65F11 and 65F12 Specific Instructions
bbr0 [],label bbr1 [],label
bbr2 [],label bbr3 [],label
bbr4 [],label bbr5 [],label
bbr6 [],label bbr7 [],label
bbs0 [],label bbs1 [],label
bbs2 [],label bbs3 [],label
bbs4 [],label bbs5 [],label
bbs6 [],label bbs7 [],label
rmb0 [] rmb1 []
rmb2 [] rmb3 []
rmb4 [] rmb5 []
rmb6 [] rmb7 []
smb0 [] smb1 []
smb2 [] smb3 []
smb4 [] smb5 []
smb6 [] smb7 []
AG.3.9 65C00/21 and 65C29 Specific Instructions
bbr0 [],label bbr1 [],label
bbr2 [],label bbr3 [],label
bbr4 [],label bbr5 [],label
bbr6 [],label bbr7 [],label
bbs0 [],label bbs1 [],label
bbs2 [],label bbs3 [],label
bbs4 [],label bbs5 [],label
bbs6 [],label bbs7 [],label
bra label
phx phy
plx ply
rmb0 [] rmb1 []
rmb2 [] rmb3 []
rmb4 [] rmb5 []
rmb6 [] rmb7 []
smb0 [] smb1 []
smb2 [] smb3 []
smb4 [] smb5 []
smb6 [] smb7 []
AS6500 ASSEMBLER PAGE AG-6
6500 INSTRUCTION SET
AG.3.10 65C02, 65C102, and 65C112 Specific Instructions
bbr0 [],label bbr1 [],label
bbr2 [],label bbr3 [],label
bbr4 [],label bbr5 [],label
bbr6 [],label bbr7 [],label
bbs0 [],label bbs1 [],label
bbs2 [],label bbs3 [],label
bbs4 [],label bbs5 [],label
bbs6 [],label bbs7 [],label
bra label
phx phy
plx ply
rmb0 [] rmb1 []
rmb2 [] rmb3 []
rmb4 [] rmb5 []
rmb6 [] rmb7 []
smb0 [] smb1 []
smb2 [] smb3 []
smb4 [] smb5 []
smb6 [] smb7 []
stz []
trb []
tsb []
Additional addressing modes for the following core instruc-
tions are also available with the 65C02, 65C102, and 65C112 pro-
cessors.
adc [] and []
cmp [] eor []
lda [] ora []
sbc [] sta []
bit [] jmp []
dec inc
APPENDIX AH
AS6800 ASSEMBLER
AH.1 6800 REGISTER SET
The following is a list of the 6800 registers used by AS6800:
a,b - 8-bit accumulators
x - index register
AH.2 6800 INSTRUCTION SET
The following tables list all 6800/6802/6808 mnemonics recog-
nized by the AS6800 assembler. The designation [] refers to a
required addressing mode argument. The following list specifies
the format for each addressing mode supported by AS6800:
#data immediate data
byte or word data
*dir direct page addressing
(see .setdp directive)
0 <= dir <= 255
,x register indirect addressing
zero offset
offset,x register indirect addressing
0 <= offset <= 255
ext extended addressing
label branch label
AS6800 ASSEMBLER PAGE AH-2
6800 INSTRUCTION SET
The terms data, dir, offset, ext, and label may all be expres-
sions.
Note that not all addressing modes are valid with every in-
struction, refer to the 6800 technical data for valid modes.
AH.2.1 Inherent Instructions
aba cba
clc cli
clv daa
des dex
ins inx
nop rti
rts sba
sec sei
sev swi
tab tap
tba tpa
tsx txs
wai
psha pshb
psh a psh b
pula pulb
pul a pul b
AH.2.2 Branch Instructions
bra label bhi label
bls label bcc label
bhs label bcs label
blo label bne label
beq label bvc label
bvs label bpl label
bmi label bge label
blt label bgt label
ble label bsr label
AS6800 ASSEMBLER PAGE AH-3
6800 INSTRUCTION SET
AH.2.3 Single Operand Instructions
asla aslb
asl a asl b
asl []
asra asrb
asr a asr b
asr []
clra clrb
clr a clr b
clr []
coma comb
com a com b
com []
deca decb
dec a dec b
dec []
inca incb
inc a inc b
inc []
lsla lslb
lsl a lsl b
lsl []
lsra lsrb
lsr a lsr b
lsr []
nega negb
neg a neg b
neg []
rola rolb
rol a rol b
rol []
rora rorb
ror a ror b
ror []
tsta tstb
tst a tst b
tst []
AS6800 ASSEMBLER PAGE AH-4
6800 INSTRUCTION SET
AH.2.4 Double Operand Instructions
adca [] adcb []
adc a [] adc b []
adda [] addb []
add a [] add b []
anda [] andb []
and a [] and b []
bita [] bitb []
bit a [] bit b []
cmpa [] cmpb []
cmp a [] cmp b []
eora [] eorb []
eor a [] eor b []
ldaa [] ldab []
lda a [] lda b []
oraa [] orab []
ora a [] ora b []
sbca [] sbcb []
sbc a [] sbc b []
staa [] stab []
sta a [] sta b []
suba [] subb []
sub a [] sub b []
AH.2.5 Jump and Jump to Subroutine Instructions
jmp [] jsr []
AS6800 ASSEMBLER PAGE AH-5
6800 INSTRUCTION SET
AH.2.6 Long Register Instructions
cpx []
lds [] sts []
ldx [] stx []
APPENDIX AI
AS6801 ASSEMBLER
AI.1 .hd6303 DIRECTIVE
Format:
.hd6303
The .hd6303 directive enables processing of the HD6303 specific
mnemonics not included in the 6801 instruction set. HD6303
mnemonics encountered without the .hd6303 directive will be
flagged with an
or errors.
BC.3.3 Arithmetic Instructions
adc (.l, .s) [],[]
add (.l, .s) [],[]
cp (.l, .s) [],[]
daa
dec (.l, .s) []
inc (.l, .s) []
mlt (.l, .s) []
neg
sbc (.l, .s) [],[]
sub (.l, .s) [],[]
ASEZ80 ASSEMBLER PAGE BC-10
EZ80 ADDRESSING AND INSTRUCTIONS
BC.3.4 Bit Manipulation Instructions
bit (.l, .s) [],[]
res (.l, .s) [],[]
set (.l, .s) [],[]
BC.3.5 Block Transfer and Compare Instructions
cpd (.l, .s) cpdr (.l, .s)
cpi (.l, .s) cpir (.l, .s)
ldd (.l, .s) lddr (.l, .s)
ldi (.l, .s) ldir (.l, .s)
BC.3.6 Exchange Instructions
ex (.l, .s) [],[]
exx
BC.3.7 Input/Output Instructions
in [],[] in0 [],[]
ind (.l, .s) indr (.l, .s)
indx (.l, .s)
ind2 (.l, .s) ind2r (.l, .s)
indm (.l, .s) indmr (.l, .s)
ini (.l, .s) inir (.l, .s)
inim (.l, .s) inimr (.l, .s)
otdm (.l, .s) otdmr (.l, .s)
otdrx (.l, .s)
otim (.l, .s) otimr (.l, .s)
otirx (.l, .s)
out (.l, .s) [],[]
out0 (.l, .s) [],[]
outd (.l, .s) otdr (.l, .s)
outd2 (.l, .s) otdr2 (.l, .s)
outi (.l, .s) otir (.l, .s)
outi2 (.l, .s) oti2r (.l, .s)
tstio []
ASEZ80 ASSEMBLER PAGE BC-11
EZ80 ADDRESSING AND INSTRUCTIONS
BC.3.8 Load Instructions
ld (.l, .s, .il, .is, .lil, .sis) [],[]
lea (.l, .s) [] pea (.l, .s) []
pop (.l, .s) [] push (.l, .s) []
BC.3.9 Logical Instructions
and (.l, .s) [],[]
cpl (.l, .s)
or (.l, .s) [],[]
tst (.l, .s) [],[]
xor (.l, .s) [],[]
BC.3.10 Processor Control Instructions
ccf di ei
halt im nop
rsmix stmix
scf slp
BC.3.11 Program Flow Instructions
call (.il, .is) []
call (.il, .is) CC,[]
djnz []
jp (.l, .s, .lil, .sis) []
jp (.l, .s, .lil, .sis) CC,[]
jr []
jr CC,[]
ret (.l)
ret (.l) CC
reti (.l)
retn (.l)
rst (.l, .s) []
ASEZ80 ASSEMBLER PAGE BC-12
EZ80 ADDRESSING AND INSTRUCTIONS
BC.3.12 Shift and Rotate Instructions
rl (.l, .s) [] rla
rlc (.l, .s) [] rlca
rld rrd
rr (.l, .s) [] rra
rrc (.1, .s) [] rrca
sla (.l, .s) []
sra (.l, .s) []
srl (.l, .s) []
APPENDIX BD
ASF2MC8 ASSEMBLER
BD.1 PROCESSOR SPECIFIC DIRECTIVES
The ASF2MC8 assembler supports the F2MC8L and F2MC8FX proces-
sor cores.
BD.1.1 .F2MC8L Directive
Format:
.F2MC8L
The .F2MC8L directive selects the F2MC8L processor cycle counts
to be listed. This is the default selection if no processor
directive is specified in the source assembly file.
BD.1.2 .F2MC8FX Directive
Format:
.F2MC8FX
The .F2MC8FX directive selects the F2MC8FX processor cycle
counts to be listed. .F2MC8L is the default selection if no
processor directive is specified in the source assembly file.
ASF2MC8 ASSEMBLER PAGE BD-2
PROCESSOR SPECIFIC DIRECTIVES
BD.1.3 The .__.CPU. Variable
The value of the pre-defined symbol '.__.CPU.' corresponds to
the selected processor type. The default value is 0 which cor-
responds to the default processor type. The following table
lists the processor types and associated values for the ASF2MC8
assembler:
Processor Type .__.CPU. Value
-------------- --------------
.F2MC8L 0
.F2MC8FX 1
The variable '.__.CPU.' is by default defined as local and
will not be output to the created .rel file. The assembler com-
mand line options -g or -a will not cause the local symbol to be
output to the created .rel file.
The assembler .globl directive may be used to change the
variable type to global causing its definition to be output to
the .rel file. The inclusion of the definition of the variable
'.__.CPU.' might be a useful means of validating that separately
assembled files have been compiled for the same processor type.
The linker will report an error for variables with multiple non
equal definitions.
BD.2 F2MC8L/F2MC8FX REGISTERS
The following is a list of register designations recognized
by the ASF2MC8 assembler:
ASF2MC8 ASSEMBLER PAGE BD-3
F2MC8L/F2MC8FX REGISTERS
pc - Program Counter
a - Accumulator
t - Temporary Accumulator
ix - Index Register
ep - Extra Pointer
sp - Stack Pointer
ps - Program Status
r0,r1,r2,r3, - Memory Registers
r4,r5,r6,r7 32 banks of
8 registers each
BD.3 F2MC8L/F2MC8FX INSTRUCTION SET
The following list specifies the format for each addressing
mode supported by ASF2MC8:
ASF2MC8 ASSEMBLER PAGE BD-4
F2MC8L/F2MC8FX INSTRUCTION SET
#data immediate data
byte or word data
*dir direct page addressing
*dir:b bit addressing to a
direct page address
ext extended addressing
a,t register addressing
pc,sp,ix,ep
@a accumulator indexed
@ix+d indexed addressing
plus offset
@ix indexed addressing
with a zero offset
@ep pointer addressing
r General-purpose registers
label call/jmp/branch label
The terms data, dir, ext, b, d, and label may all be expres-
sions.
Note that not all addressing modes are valid with every in-
struction, refer to the F2MC8L/F2MC8FX technical data for valid
modes.
The following tables list all F2MC8L/F2MC8FX mnemonics recog-
nized by the ASF2MC8 assembler. The designation [] refers to a
required addressing mode argument.
ASF2MC8 ASSEMBLER PAGE BD-5
F2MC8L/F2MC8FX INSTRUCTION SET
BD.3.1 Transfer Instructions
mov [],[] movw [],[]
xch [],[] xchw [],[]
clrb [] setb []
swap []
BD.3.2 Operation Instructions
addc a(,[]) addcw a
subc a(,[]) subcw a
inc r incw []
dec r decw []
mulu a divu a
and a(,[]) andw a
cmp a(,[]) cmpw a
or a(,[]) orw a
xor a(,[]) xorw a
rolc a rorc a
daa das
BD.3.3 Branch/Jump/Call Instructions
bz label bew label
bnz label bne label
bc label blo label
bnc label bhs label
bn label bp label
blt label bge label
bbc *dir:b,label bbs *dir:b,label
jmp [] call label
callv #data xchw a,pc
ret reti
BD.3.4 Other Instructions
pushw [] popw []
nop
clrc setc
clri seti
APPENDIX BE
ASF8 ASSEMBLER
The AS8 assembler supports the F8 and 3870 processor cores.
BE.1 F8 REGISTERS
The following is a list of register designations recognized
by the ASF8 assembler:
ASF8 ASSEMBLER PAGE BE-2
F8 REGISTERS
r0-r11 - Registers
j - Scratch Pad Register r9
hu - MSB of register H the
Data Counter Buffer Register
Scratch Pad Register r10
hl - LSB of register H the
Data Counter Buffer Register
Scratch Pad Register r11
ku - MSB of register K the
Stack Buffer Register
kl - LSB of register K the
Stack Buffer Register
qu - MSB of register Q a
Buffer Register for the
Data Counter or Program Counter
ql - LSB of register Q a
Buffer Register for the
Data Counter or Program Counter
a - Accumulator
is - Scratch Pad Address Register (ISAR)
w - Status Register
s - Register Addressed
by is (unchanged)
i - Register Addressed
by is (incremented)
d - Register Addressed
by is (decremented)
pc0 - Program Counter
or p0, pc
pc1 - Program Counter Buffer or
or p1, p Stack Register
dc0 - Data Counter
or d0, dc
ASF8 ASSEMBLER PAGE BE-3
F8 INSTRUCTION SET
BE.2 F8 INSTRUCTION SET
The following list specifies the format for each addressing
mode supported by ASF8:
#nibble immediate 4-Bit data
#byte immediate 8-Bit data
#word immediate 16-Bit data
#t3 3-Bit test condition
[Zero Carry Sign]
#t4 4-Bit test condition
[Overflow Zero Carry Sign]
r register r0-r11 addressing and
indirect addressing s, i, and d
j is equivalent to r9
hu (MSB of h) is equivalent to r10
hl (LSB of h) is equivalent to r11
ku and kl MSB and LSB of k register
qu and ql MSB and LSB of q register
h, k, or q 16-Bit registers
p0, pc0, or pc
p1 or p
d0, dc0, or dc
w status register
is Indirect Scratchpad Address Register
label call/jmp/branch label
The terms nibble, byte, word, t3, t4, and label may all be ex-
pressions.
The following tables list all F8 mnemonics recognized by the
ASF8 assembler.
ASF8 ASSEMBLER PAGE BE-4
F8 INSTRUCTION SET
BE.2.1 Accumulator Group Instructions
lnk ai #byte
ni #byte clr
ci #byte com
xi #byte inc
li #byte lis #nibble
oi #byte sl 1
sl 4 sr 1
sr 4
BE.2.2 Branch Instructions
bc label bp label
bz label bt #t3,label
bm label bnc label
bno label bnz label
bf #t4,label br7 label
br label jmp label
BE.2.3 Memory Reference Instructions
am amd
nm cm
xm lm
om st
BE.2.4 Address Register Instructions
adc pk
pi #word xdc
lr dc,q lr dc,h
dci #word lr p0,q
lr p,k pop
lr q,dc lr h,dc
lr k,p
ASF8 ASSEMBLER PAGE BE-5
F8 INSTRUCTION SET
BE.2.5 Scratchpad Register Instructions
as r asd r
ds r
lr a,r
lr a,ku lr a,kl
lr a,qu lr a,ql
lr r,a
lr ku,a lr kl,a
lr qu,a lr ql,a
ns r xs r
BE.2.6 Miscellaneous Instructions
di ei
in #byte ins #nibble
out #byte outs #nibble
lr is,a lr a,is
lr w,j lr j,w
lisl #0-#7 lisu #0-#7
nop
APPENDIX BF
ASGB ASSEMBLER
BF.1 ACKNOWLEDGEMENT
Thanks to Roger Ivie for his contribution of the ASGB cross
assembler.
Roger Ivie
ivie at cc dot usu dot edu
BF.2 INTRODUCTION
The Gameboy uses an 8-bit processor which is closely related
to the 8080. It is usually described as a modified Z80, but may
be more closely understood as an enhanced 8080; it has the 8080
register set and many, but not all, enhanced Z80 instructions.
However, even this is not accurate, for the Gameboy also lacks
some basic 8080 instructions (most annoyingly SHLD and LHLD).
ASGB is based on ASZ80 and therefore uses the Z80 mnemonic set.
ASGB ASSEMBLER PAGE BF-2
GAMEBOY REGISTER SET AND CONDITIONS
BF.3 GAMEBOY REGISTER SET AND CONDITIONS
The following is a complete list of register designations and
condition mnemonics:
byte registers - a,b,c,d,e,h,l
register pairs - af, bc, de, hl
word registers - pc, sp
C - carry bit set
NC - carry bit clear
NZ - zero bit clear
Z - zero bit set
BF.4 GAMEBOY INSTRUCTION SET
The following tables list all Gameboy mnemnoics recognized by
the ASGB assembler. The designation [] refers to a required ad-
dressing mode argument. The following list specifies the format
for each addressing mode supported by ASGB:
#data immediate data
byte or word data
n byte value
rg a byte register
a,b,c,d,e,h,l
rp a register pair or 16-bit register
bc,de,hl
(hl) implied addressing or
register indirect addressing
(label) direct addressing
label call/jmp/jr label
The terms data, dir, and ext may all be expression. The term
dir is not allowed to be an external reference.
Note that not all addressing modes are valid with every in-
struction. Although official information is not, as far as I
ASGB ASSEMBLER PAGE BF-3
GAMEBOY INSTRUCTION SET
know, publically available for the Gameboy processor, many
unofficial sources are available on the internet.
BF.4.1 .tile Directive
Format:
.tile /string/ or
.tile ^/string/
where: string is a string of ascii characters taken from the
set ' ', '.', '+', '*', '0', '1', '2', and '3'.
The string must be a multiple of eight
characters long.
/ / represent the delimiting characters. These
delimiters may be any paired printing
characters, as long as the characters are not
contained within the string itself. If the
delimiting characters do not match, the .tile
directive will give the
error.
The Gameboy displays information on the screen using a pro-
grammable character set (referred to as "tiles" among Gameboy
developers). The ASGB cross assembler has a processor-specific
assembler directive to aid in the creation of the game's
character set.
Each character is created from an 8x8 grid of pixels, each
pixel of which is composed of two bits. The .tile directive ac-
cepts a single string argument which is processed to create the
byte values corresponding to the lines of pixels in the
character. The string argument must be some multiple of 8
characters long, and be one of these characters:
' ' or '0' - for the pixel value 00
'.' or '1' - for the pixel value 01
'+' or '2' - for the pixel value 10
'*' or '3' - for the pixel value 11
The .tile directive processes each 8-character group of its
string argument to create the two-byte value corresponding to
that line of pixels. The example in the popular extant
literature could be done using ASGB like this:
ASGB ASSEMBLER PAGE BF-4
GAMEBOY INSTRUCTION SET
0000 7C 7C 1 .tile " ***** "
0002 00 C6 2 .tile "++ ++ "
0004 C6 00 3 .tile ".. .. "
0006 00 FE 4 .tile "+++++++ "
0008 C6 C6 5 .tile "** ** "
000A 00 C6 6 .tile "++ ++ "
000C C6 00 7 .tile ".. .. "
000E 00 00 8 .tile " "
Or, using the synonym character set, as:
0010 7C 7C 10 .tile "03333300"
0012 00 C6 11 .tile "22000220"
0014 C6 00 12 .tile "11000110"
0016 00 FE 13 .tile "22222220"
0018 C6 C6 14 .tile "33000330"
001A 00 C6 15 .tile "22000220"
001C C6 00 16 .tile "11000110"
001E 00 00 17 .tile "00000000"
Since .tile is perfectly willing to assemble multiple lines
of a character at once (as long as it is given complete rows of
pixels), it could even be done as:
.tile " ***** ++ ++ .. .. +++++++ "
.tile "** ** ++ ++ .. .. "
BF.4.2 Potentially Controversial Mnemonic Selection
Although the Gameboy processor is based on the Z80, it does
include some features which are not present in the Z80. The Z80
mnemonic set is not sufficient to describe these additional
operations; mnemonics must be created for the new operations.
The mnemonics ASGB uses are not the same as those used by other
publically-available Gameboy assemblers.
ASGB ASSEMBLER PAGE BF-5
GAMEBOY INSTRUCTION SET
BF.4.2.1 Auto-Indexing Loads -
The Gameboy provides instructions to load or store the ac-
cumulator indirectly via HL and then subsequently increment or
decrement HL. ASGB uses the mnemonic 'ldd' for the instructions
which decrement HL and 'ldi' for the instructions which incre-
ment HL. Because the Gameboy lacks the Z80's block moves, the
mnemonics are not otherwise needed by ASGB.
ldd a,(hl) ldd (hl),a
ldi a,(hl) ldi (hl),a
BF.4.2.2 Input and Output Operations -
The Gameboy replaces the Z80's separate address space for
I/O with a mechanism similar to the zero page addressing of pro-
cessors such as the 6800 or 6502. All I/O registers in the
Gameboy reside in the address range between 0xff00 and 0xffff.
The Gameboy adds special instructions to load and store the ac-
cumulator from and into this page of memory. The instructions
are analogous to the Z80's in and out instructions and ASGB re-
tains the 'in' and 'out' mnemonics for them.
in a,(n) out (n),a
in a,(c) out (c),a
From ASGB's perspective, the RAM available from 0xff80
through 0xffff is composed of unused I/O locations rather than
direct-page RAM.
BF.4.2.3 The 'stop' Instruction -
The publically-available documentation for the Gameboy
lists the 'stop' instruction as the two-byte instruction 10 00,
and the other freely-available Gameboy assemblers assemble it in
that manner. As far as I can tell, the only rationale for this
is that the corresponding Z80 instruction ('djnz label') is a
two-byte instruction. ASGB assembles 'stop' as the one-byte in-
struction 10.
ASGB ASSEMBLER PAGE BF-6
GAMEBOY INSTRUCTION SET
BF.4.3 Inherent Instructions
ccf cpl
daa di
ei nop
halt rla
rlca rra
rrca scf
reti stop
swap
BF.4.4 Implicit Operand Instructions
adc a,[] adc []
add a,[] add []
and a,[] and []
cp a,[] cp []
dec a,[] dec []
inc a,[] inc []
or a,[] or []
rl a,[] rl []
rlc a,[] rlc []
rr a,[] rr []
rrc a,[] rrc []
sbc a,[] sbc []
sla a,[] sla []
sra a,[] sra []
srl a,[] srl []
sub a,[] sub []
xor a,[] xor []
BF.4.5 Load Instructions
ld rg,[] ld [],rg
ld (bc),a ld a,(bc)
ld (de),a ld a,(de)
ld (label),a ld a,(label)
ld (label),sp ld rp,#data
ld sp,hl ld hl,sp
ldd a,(hl) ldd (hl),a
ldi a,(hl) ldi (hl),a
ASGB ASSEMBLER PAGE BF-7
GAMEBOY INSTRUCTION SET
BF.4.6 Call/Return Instructions
call C,label ret C
call NC,label ret NC
call Z,label ret Z
call NZ,label ret NZ
call label ret
rst n
BF.4.7 Jump Instructions
jp C,label jp NC,label
jp Z,label jp NZ,label
jp (hl) jp label
jr C,label jr NC,label
jr Z,label jr NZ,label
jr label
BF.4.8 Bit Manipulation Instructions
bit n,[]
res n,[]
set n,[]
BF.4.9 Input and Output Instructions
in a,(n) in a,(c)
out (n),a out (c),a
ASGB ASSEMBLER PAGE BF-8
GAMEBOY INSTRUCTION SET
BF.4.10 Register Pair Instructions
add hl,rp add hl,sp
add sp,#data
push rp pop rp
APPENDIX BG
ASH8 ASSEMBLER
BG.1 H8/3XX REGISTER SET
The following is a list of the H8 registers used by ASH8:
r0 - r7,sp 16-bit accumulators
r0L - r7L,spL 8-bit accumulators
r0H - r7H,spH 8-bit accumulators
spL,spH,sp stack pointers
ccr condition code
BG.2 H8/3XX INSTRUCTION SET
The following tables list all H8/3xx mnemonics recognized
by the ASH8 assembler. The designation [] refers to a required
addressing mode argument. The following list specifies the
format for each addressing mode supported by ASH8:
#xx:3 immediate data (3 bit)
#xx:8 immediate data (8 bit)
#xx:16 immediate data (16 bit)
*dir direct page addressing
(see .setdp directive)
0xFF00 <= dir <= 0xFFFF
label branch label
rn registers (16 bit)
r0-r7,sp
ASH8 ASSEMBLER PAGE BG-2
H8/3XX INSTRUCTION SET
rnB registers (8 bit)
r0H-r7H,r0L-r7L,spH,spL
ccr condition code register
@rn register indirect
@-rn register indirect (auto pre-decrement)
@rn+ register indirect (auto post-increment)
@[offset,rn] register indirect, 16-bit displacement
@@offset memory indirect, (8-bit address)
ext extended addressing (16-bit)
The terms data, dir, label, offset, and ext may all be expres-
sions.
Note that not all addressing modes are valid with every in-
struction, refer to the H8/3xx technical data for valid modes.
BG.2.1 Inherent Instructions
eepmov
nop
sleep
rte
rts
ASH8 ASSEMBLER PAGE BG-3
H8/3XX INSTRUCTION SET
BG.2.2 Branch Instructions
bcc label bcs label
beq label bf label
bge label bgt label
bhi label bhis label
bhs label ble label
blo label blos label
bls label blt label
bmi label bne label
bpl label bra label
brn label bt label
bvc label bvs label
bsr label
ASH8 ASSEMBLER PAGE BG-4
H8/3XX INSTRUCTION SET
BG.2.3 Single Operand Instructions
Free Form
daa rnB das rnB
dec rnB inc rnB
neg rnB not rnB
rotxl rnB rotxr rnB
rotl rnB rotr rnB
shal rnB shar rnB
shll rnB shlr rnB
push rn pop rn
Byte / Word Form
daa.b rnB das.b rnB
dec.b rnB inc.b rnB
neg.b rnB not.b rnB
rotxl.b rnB rotxr.b rnB
rotl.b rnB rotr.b rnB
shal.b rnB shar.b rnB
shll.b rnB shlr.b rnB
push.w rn pop.w rn
ASH8 ASSEMBLER PAGE BG-5
H8/3XX INSTRUCTION SET
BG.2.4 Double Operand Instructions
Free Form
add rnB,rnB add #xx:8,rnB
add rn,rn
adds #1,rn adds #2,rn
addx rnB,rnB addx #xx:8,rnB
cmp rnB,rnB cmp #xx:8,rnB
cmp rn,rn
sub rnB,rnB
sub rn,rn
subs #1,rn subs #2,rn
subx rnB,rnB subx #xx:8,rnB
and rnB,rnB and #xx:8,rnB
and #xx:8,ccr
or rnB,rnB or #xx:8,rnB
or #xx:8,ccr
xor rnB,rnB xor #xx:8,rnB
xor #xx:8,ccr
Byte / Word Form
add.b rnB,rnB add.b #xx:8,rnB
add.w rn,rn
cmp.b rnB,rnB cmp.b #xx:8,rnB
cmp.w rn,rn
sub.b rnB,rnB
sub.w rn,rn
addx.b rnB,rnB addx.b #xx:8,rnB
and.b rnB,rnB and.b #xx:8,rnB
and.b #xx:8,ccr
or.b rnB,rnB or.b #xx:8,rnB
or.b #xx:8,ccr
subx.b rnB,rnB subx.b #xx:8,rnB
xor.b rnB,rnB xor.b #xx:8,rnB
ASH8 ASSEMBLER PAGE BG-6
H8/3XX INSTRUCTION SET
xor.b #xx:8,ccr
ASH8 ASSEMBLER PAGE BG-7
H8/3XX INSTRUCTION SET
BG.2.5 Mov Instructions
Free Form
mov rnB,rnB mov rn,rn
mov #xx:8,rnB mov #xx:16,rn
mov @rn,rnB mov @rn,rn
mov @[offset,rn],rnB mov @[offset,rn],rn
mov @rn+,rnB mov @rn+,rn
mov @dir,rnB
mov dir,rnB
mov *@dir,rnB
mov *dir,rnB
mov @label,rnB mov @label,rn
mov label,rnB mov label,rn
mov rnB,@rn mov rn,@rn
mov rnB,@[offset,rn] mov rn,@[offset,rn]
mov rnB,@-rn mov rn,@-rn
mov rnB,@dir
mov rnB,dir
mov rnB,*@dir
mov rnB,*dir
mov rnB,@label mov rn,@label
mov rnB,label mov rn,label
Byte / Word Form
mov.b rnB,rnB mov.w rn,rn
mov.b #xx:8,rnB mov.w #xx:16,rn
mov.b @rn,rnB mov.w @rn,rn
mov.b @[offset,rn],rnB mov.w @[offset,rn],rn
mov.b @rn+,rnB mov.w @rn+,rn
mov.b @dir,rnB
mov.b dir,rnB
mov.b *@dir,rnB
mov.b *dir,rnB
mov.b @label,rnB mov.w @label,rn
mov.b label,rnB mov.w label,rn
mov.b rnB,@rn mov.w rn,@rn
mov.b rnB,@[offset,rn] mov.w rn,@[offset,rn]
mov.b rnB,@-rn mov.w rn,@-rn
mov.b rnB,@dir
mov.b rnB,dir
mov.b rnB,*@dir
mov.b rnB,*dir
mov.b rnB,@label mov.w rn,@label
mov.b rnB,label mov.w rn,label
ASH8 ASSEMBLER PAGE BG-8
H8/3XX INSTRUCTION SET
BG.2.6 Bit Manipulation Instructions
bld #xx:3,rnB bld #xx:3,@rn
bld #xx:3,@dir bld #xx:3,dir
bld #xx:3,*@dir bld #xx:3,*dir
bild #xx:3,rnB bild #xx:3,@rn
bild #xx:3,@dir bild #xx:3,dir
bild #xx:3,*@dir bild #xx:3,*dir
bst #xx:3,rnB bst #xx:3,@rn
bst #xx:3,@dir bst #xx:3,dir
bst #xx:3,*@dir bst #xx:3,*dir
bist #xx:3,rnB bist #xx:3,@rn
bist #xx:3,@dir bist #xx:3,dir
bist #xx:3,*@dir bist #xx:3,*dir
band #xx:3,rnB band #xx:3,@rn
band #xx:3,@dir band #xx:3,dir
band #xx:3,*@dir band #xx:3,*dir
biand #xx:3,rnB biand #xx:3,@rn
biand #xx:3,@dir biand #xx:3,dir
biand #xx:3,*@dir biand #xx:3,*dir
bor #xx:3,rnB bor #xx:3,@rn
bor #xx:3,@dir bor #xx:3,dir
bor #xx:3,*@dir bor #xx:3,*dir
bior #xx:3,rnB bior #xx:3,@rn
bior #xx:3,@dir bior #xx:3,dir
bior #xx:3,*@dir bior #xx:3,*dir
bxor #xx:3,rnB bxor #xx:3,@rn
bxor #xx:3,@dir bxor #xx:3,dir
bxor #xx:3,*@dir bxor #xx:3,*dir
bixor #xx:3,rnB bixor #xx:3,@rn
bixor #xx:3,@dir bixor #xx:3,dir
bixor #xx:3,*@dir bixor #xx:3,*dir
ASH8 ASSEMBLER PAGE BG-9
H8/3XX INSTRUCTION SET
BG.2.7 Extended Bit Manipulation Instructions
bset #xx:3,rnB bset #xx:3,@rn
bset #xx:3,@dir bset #xx:3,dir
bset #xx:3,*@dir bset #xx:3,*dir
bset rnB,rnB bset rnB,@rn
bset rnB,@dir bset rnB,dir
bset rnB,*@dir bset rnB,*dir
bclr #xx:3,rnB bclr #xx:3,@rn
bclr #xx:3,@dir bclr #xx:3,dir
bclr #xx:3,*@dir bclr #xx:3,*dir
bclr rnB,rnB bclr rnB,@rn
bclr rnB,@dir bclr rnB,dir
bclr rnB,*@dir bclr rnB,*dir
bnot #xx:3,rnB bnot #xx:3,@rn
bnot #xx:3,@dir bnot #xx:3,dir
bnot #xx:3,*@dir bnot #xx:3,*dir
bnot rnB,rnB bnot rnB,@rn
bnot rnB,@dir bnot rnB,dir
bnot rnB,*@dir bnot rnB,*dir
btst #xx:3,rnB btst #xx:3,@rn
btst #xx:3,@dir btst #xx:3,dir
btst #xx:3,*@dir btst #xx:3,*dir
btst rnB,rnB btst rnB,@rn
btst rnB,@dir btst rnB,dir
btst rnB,*@dir btst rnB,*dir
BG.2.8 Condition Code Instructions
andc #xx:8,ccr andc #xx:8
and #xx:8,ccr and.b #xx:8,ccr
ldc #xx:8,ccr ldc #xx:8
ldc rnB,ccr ldc rnB
orc #xx:8,ccr orc #xx:8
or #xx:8,ccr or.b #xx:8,ccr
xorc #xx:8,ccr xorc #xx:8
xor #xx:8,ccr xor.b #xx:8,ccr
stc ccr,rnB stc rnB
ASH8 ASSEMBLER PAGE BG-10
H8/3XX INSTRUCTION SET
BG.2.9 Other Instructions
divxu rnB,rn divxu.b rnB,rn
mulxu rnB,rn mulxu.b rnB,rn
movfpe @label,rnB movfpe label,rnB
movfpe.b @label,rnB movfpe.b label,rnB
movtpe @label,rnB movtpe label,rnB
movtpe.b @label,rnB movtpe.b label,rnB
BG.2.10 Jump and Jump to Subroutine Instructions
jmp @rn jmp @@dir
jmp @label jmp label
jsr @rn jsr @@dir
jsr @label jsr label
APPENDIX BH
ASM8C ASSEMBLER
BH.1 M8C REGISTER SET
The following is a list of the M8C registers used by ASM8C:
A - Accumulator
X - Index
SP - Stack Pointer
F - Flags
BH.2 M8C ADDRESSING MODES
The M8C instructions may have none, one, or two operands
selected from the registers listed above or an addressing mode
from the following list:
expr - immediate argument
- In the lcall, ljmp, index,
and pc relative branching
instructions expr is an
address expression.
#expr - immediate argument
[expr] - argument at location expr
[x+expr] - argument at location x + expr
reg[expr] - argument at location expr
in register space
reg[x+expr] - argument at location x + expr
in register space
[[expr]++] - The value in memory at address
expr (the indirect address)
points to a memory location in
RAM. The value in memory at
ASM8C ASSEMBLER PAGE BH-2
M8C ADDRESSING MODES
address expr is then incremented.
This addressing mode is used only
by the mvi instruction and
allows the short form [expr]
for this addressing mode.
BH.3 M8C INSTRUCTION SET
The following tables list all M8C mnemonics and addressing
modes recognized by the ASM8C assembler.
BH.3.1 Double Operand Arithmetic Instructions
adc a,expr
adc a,[expr] adc [expr],a
adc a,[x+expr] adc [x+expr],a
adc [expr],expr adc [x+expr],expr
add a,expr
add a,[expr] add [expr],a
add a,[x+expr] add [x+expr],a
add [expr],expr add [x+expr],expr
add sp,expr
cmp a,expr
cmp a,[expr]
cmp a,[x+expr]
cmp [expr],expr cmp [x+expr],expr
sbb a,expr
sbb a,[expr] sbb [expr],a
sbb a,[x+expr] sbb [x+expr],a
sbb [expr],expr sbb [x+expr],expr
sub a,expr
sub a,[expr] sub [expr],a
sub a,[x+expr] sub [x+expr],a
sub [expr],expr sub [x+expr],expr
ASM8C ASSEMBLER PAGE BH-3
M8C INSTRUCTION SET
BH.3.2 Double Operand Logic Instructions
and a,expr and f,expr
and a,[expr] and [expr],a
and a,[x+expr] and [x+expr],a
and [expr],expr and [x+expr],expr
and reg[expr],expr and reg[x+expr],expr
or a,expr or f,expr
or a,[expr] or [expr],a
or a,[x+expr] or [x+expr],a
or [expr],expr or [x+expr],expr
or reg[expr],expr or reg[x+expr],expr
xor a,expr xor f,expr
xor a,[expr] xor [expr],a
xor a,[x+expr] xor [x+expr],a
xor [expr],expr xor [x+expr],expr
xor reg[expr],expr xor reg[x+expr],expr
BH.3.3 Miscellaneous Double Operand Instructions
swap a,x swap a,sp
swap a,[expr] swap a,[x+expr]
tst [expr] tst [x+expr]
tst reg[expr] tst reg[x+expr]
BH.3.4 Single Operand Shift/Rotate Instructions
asl a
asl [expr] asl [x+expr]
asr a
asr [expr] asr [x+expr]
rlc a
rlc [expr] rlc [x+expr]
rrc a
rrc [expr] rrc [x+expr]
ASM8C ASSEMBLER PAGE BH-4
M8C INSTRUCTION SET
BH.3.5 Miscellaneous Single Operand Instructions
cpl a
dec a dec x
dec [expr] dec [x+expr]
inc a inc x
inc [expr] inc [x+expr]
pop a pop x
push a push x
tst [expr] tst [x+expr]
tst reg[expr] tst reg[x+expr]
BH.3.6 Move Instructions
mov a,x
mov a,expr
mov a,[expr] mov [expr],a
mov a[x+expr] mov [x+expr],a
mov x,a mov x,sp
mov x,expr
mov x,[expr] mov [expr],x
mov x,[x+expr]
mov [expr],expr mov [x+expr],expr
mov [expr],[expr]
mov a,reg[expr] mov a,reg[x+expr]
mov reg[expr],a mov reg[x+expr],a
mov reg[expr],expr mov reg[x+expr],expr
mvi a,[expr] == mvi a,[[expr]++]
mvi [expr],a == mvi [[expr]++],a
ASM8C ASSEMBLER PAGE BH-5
M8C INSTRUCTION SET
BH.3.7 Inherent Instructions
halt nop
romx ssc
ret reti
BH.3.8 Branching Instructions
lcall expr ljmp expr
jz expr jnz expr
jc expr jnc expr
jacc expr
BH.3.9 Relative Table Read Instruction
index expr
APPENDIX BI
ASPIC ASSEMBLER
BI.1 PIC ASSEMBLER NOTES
The PIC 12,14,16, and 17 series of processors uses a non
unified addressing scheme: the instruction addressing is 1 per
instruction word, each instruction uses a word of memory varying
from 12 to 16 bits in length. The processor data is addressed
as 1 per byte of data. To properly address the program/data
spaces you, the programmer, must seperate your program and data
into seperate code and data areas. The data area is addressed
as 1 per byte and the code area is addressed as 1 per instruc-
tion. The assembler/linker processes the instruction code so
that the linker will output 2 bytes for each instruction word.
The instruction word address will be the file encoded address
divided by 2.
The pic 18 series of processors uses a unified addressing
scheme: the instruction and data addressing is 1 per 8-bit
byte. The assembler/linker processes the instruction code so
that the linker will output 2 bytes for each instruction word.
The byte ordering is low-byte then high-byte and the program ad-
dress is the the file encoded address.
ASPIC ASSEMBLER PAGE BI-2
PROCESSOR SPECIFIC DIRECTIVES
BI.2 PROCESSOR SPECIFIC DIRECTIVES
The ASPIC assembler has several processor specific assem-
bler directives. These directives specify a processor name,
select a PIC processor family type, define the maximum ram ad-
dress, specify ram addresses that should not be accessed, and
define the register file address page.
BI.2.1 .pic Directive
Format:
.pic /string/ or
.pic ^/string/
where: string represents a text string. The string is the pic
processor type.
/ / represent the delimiting characters. These
delimiters may be any paired printing
characters, as long as the characters are not
contained within the string itself. If the
delimiting characters do not match, the .pic
directive will give the
error.
The assembler uses the delimited string to define a proces-
sor specific symbol. e.g: "p12c508" produces the symbol
__12c508 having a value of 1. This symbol can then be used in
an .ifdef/.else/.endif construct.
The assembler should be configured by including directives
similiar to the folowing at the beginning of your assembly file:
.pic "p12c508" ; Set PIC Name
.pic12bit ; Select PIC Type
The ASPIC assembler will then be configured for the PIC
processor type "p12c508". The .pic directive must precede the
PIC type directive. The PIC type directive configures the as-
sembler based on the processor name and type selection.
An alternate method to configure the ASPIC assembler is as
follows:
.pic "p12c508" ; Set PIC Name
ASPIC ASSEMBLER PAGE BI-3
PROCESSOR SPECIFIC DIRECTIVES
.include "piccpu.def" ; Selects PIC Type
To define the special function register names, bit values,
and memory constraints for a specific processor include the
appropriate definition file:
.include "p12c508.def" ; Definitions
BI.2.2 .picnopic Directive
Format:
.picnopic
This directive deselects all processor specific mnemonics.
BI.2.3 .pic12bit Directive
Format:
.pic12bit
This directive selects the 12-bit instruction word mnemon-
ics and opcode values to be used during the assembly process.
BI.2.4 .pic14bit Directive
Format:
.pic14bit
This directive selects the 14-bit instruction word mnemon-
ics and opcode values to be used during the assembly process.
ASPIC ASSEMBLER PAGE BI-4
PROCESSOR SPECIFIC DIRECTIVES
BI.2.5 .pic16bit Directive
Format:
.pic16bit
This directive selects the 16-bit instruction word mnemon-
ics and opcode values to be used during the assembly process.
BI.2.6 .pic20bit Directive
Format:
.pic20bit
This directive selects 20-bit addressing and the 16-bit in-
struction word mnemonics and opcode values to be used during the
assembly process.
BI.2.7 .picfix Directive
Format:
.picfix chip, mnemonic, value
This directive can be used to "fix" or change the opcode
value of any pic instruction of the currently selected pic type.
e.g.:
.picfix "p12c671", "clrw", 0x0103
will change the "clrw" instruction's opcode to 0x0103 if the
current pic type is "p12c671".
ASPIC ASSEMBLER PAGE BI-5
PROCESSOR SPECIFIC DIRECTIVES
BI.2.8 .picgoto Directive
Format:
.picgoto (optional argument)
This directive selects the PIC or ASxxxx mode of CALL, GOTO
and Branching argument processing. The default ASxxxx mode,
specified by a zero valued argument, processes the instruction
arguments as regular labels (with relocation if required). A
blank or non-zero argument invokes the PIC mode. The PIC mode
inserts the value of the instruction argument directly into the
instruction without further processing.
BI.2.9 .maxram Directive
Format:
.maxram value
Where value is the highest allowed ram address
BI.2.10 .badram Directive
Format:
.badram address
.badram lo:hi
Where address is a single location and lo:hi is a range of
addresses that should not be used. Multiple locations and/or
ranges may be specified by seperating the arguments with a
comma:
.badram 0x23, 0x28:0x2F, ...
The ASPIC assembler will report an error for any absolute
register file address in the badram range.
ASPIC ASSEMBLER PAGE BI-6
PROCESSOR SPECIFIC DIRECTIVES
BI.2.11 .setdmm Directive
Format:
.setdmm value
The .setdmm (set Data Memory Map) directive is used to in-
form the assembler and linker about which ram bank has been
selected for access. The PIC17Cxxx microprocessor family allows
upto 2 (or more) banks of 256 byte ram blocks. The PIC18Cxxx
microprocessor family allows upto 16 banks of 256 byte ram
blocks. The data memory map value must be set on a 256 byte
boundary. e.g.:
.setdmm 0x0F00
The assembler verifies that any absolute address to the
register file is within the 256 byte page. External direct
references are assumed by the assembler to be in the correct
area and have valid offsets. The linker will check all page
relocations to verify that they are within the correct address-
ing range.
BI.2.12 The .__.CPU. Variable
The value of the pre-defined symbol '.__.CPU.' corresponds
to the selected processor type. The default value is 0 which
corresponds to the default processor type. The following table
lists the processor types and associated values for the ASPIC
assembler:
Processor Type .__.CPU. Value
-------------- --------------
.picnopic 0
.pic12bit 1
.pic14bit 2
.pic16bit 3
.pic20bit 4
The variable '.__.CPU.' is by default defined as local and
will not be output to the created .rel file. The assembler com-
mand line options -g or -a will not cause the local symbol to be
output to the created .rel file.
ASPIC ASSEMBLER PAGE BI-7
PROCESSOR SPECIFIC DIRECTIVES
The assembler .globl directive may be used to change the
variable type to global causing its definition to be output to
the .rel file. The inclusion of the definition of the variable
'.__.CPU.' might be a useful means of validating that seperately
assembled files have been compiled for the same processor type.
The linker will report an error for variables with multiple non
equal definitions.
BI.3 12-BIT OPCODE PIC
The 12-bit opcode family of PIC processors support the following
assembler arguments:
(*)f
(*)f,(#)d
(*)f,(#)b
(#)k
label
where: f register file address
d destination select:
(0, -> w), (1 -> f)
the letters w or f may be used
to select the destination
b bit address in an 8-bit file register
k literal constant
label label name
Items enclosed in () are optional.
The terms f, d, b, k, and label may all be expressions.
Note that not all addressing modes are valid with every in-
struction, refer to the processor specific technical data for
valid modes.
PIC12C5XX CPU Type
PIC12C508, PIC12C509, PIC12CE518
PIC12C508A, PIC12C509A, PIC12CE519
PIC12CR509A
ASPIC ASSEMBLER PAGE BI-8
14-BIT OPCODE PIC
BI.4 14-BIT OPCODE PIC
The 14-bit opcode family of PIC processors support the following
assembler arguments:
(*)f
(*)f,(#)d
(*)f,(#)b
(#)k
label
where: f register file address
d destination select:
(0, -> w), (1 -> f)
the letters w or f may be used
to select the destination
b bit address in an 8-bit file register
k literal constant
label label name
Items enclosed in () are optional.
The terms f, d, b, k, and label may all be expressions.
Note that not all addressing modes are valid with every in-
struction, refer to the processor specific technical data for
valid modes.
PIC12C67X CPU Type
PIC12C671, PIC12C672, PIC12LC671,
PIC12LC672
PIC12CE673, PIC12CE674, PIC12LCE673,
PIC12LCE674
PIC14000 CPU Type
PIC14000
PIC16C15X CPU Type
PIC16C154, PIC16C156, PIC16C158
PIC16CR154, PIC16CR156, PIC16CR158
PIC16C5X CPU Type
PIC16C52
PIC16C54, PICC16C54A, PIC16C54B,
PIC16C54C
PIC16CR54, PIC16CR54A, PIC16C54B,
PIC16CR54C
ASPIC ASSEMBLER PAGE BI-9
14-BIT OPCODE PIC
PIC16C55, PIC16C55A, PIC16C56,
PIC16C56A
PIC16CR56A
PIC16C57, PIC16CR57A, PIC16C57B,
PIC16C57C
PIC16C58A, PIC16CR58A, PIC16C58B,
PIC16CR58B
PIC16C55X CPU Type
PIC16C554, PIC16C556, PIC16C558
PIC16C62X, PIC16C64X and, PIC16C66X CPU Types
PIC16C620, PIC16C621, PIC16C622
PIC16C642, PIC16C662
PIC16C7XX CPU Type
PIC16C71, PIC16C72, PIC16CR72
PIC16C73A, PIC16C74A, PIC16C76, PIC16C77
PIC16C710, PIC16C711, PIC16C715
PIC16C8X CPU Type
PIC16F83, PIC16CR83, PIC16F84,
PIC16CR84
PIC16HV540
PIC16F627, PIC16F628
PIC16F870, PIC16F871, PIC16F872,
PIC16F873
PIC16F874, PIC16F876, PIC16F877
PIC16C9XX CPU Type
PIC16C923, PIC16C924
BI.5 16-BIT OPCODE PIC
The 16-bit opcode family of PIC processors support the following
assembler arguments:
(*)f
(*)f,(#)d
(*)f,(#)s
(*)f,(#)b
(*)f,(*)p / (*)p,(*)f
(#)t,(*)f
(#)t,(#)i,(*)f
{#}k
label
where: f register file address
ASPIC ASSEMBLER PAGE BI-10
16-BIT OPCODE PIC
d destination select:
(0, -> w), (1 -> f)
the letters w or f may be used
to select the destination
s destination select:
(0, -> f and w), (1, -> f)
the letters w or f may be used
to select the destination
t table byte select:
(0, -> lower byte)
(1, -> upper byte)
i table pointer control
(0, -> no change)
(1, -> post increment)
b bit address of an 8-bit file register
p peripheral register file address
k literal constant
label label name
Items enclosed in () are optional.
The terms f, d, s, t, i, b, p, k, and label may all be
expressions.
Note that not all addressing modes are valid with every in-
struction, refer to the processor specific technical data for
valid modes.
PIC17CXXX CPU Type
PIC17C42, PIC17C42A, PIC17C43, PIC17C44
PIC17C752, PIC17C756, PIC17C756A
PIC17C762, PIC17C766, PIC17CR42,
PIC17CR43
BI.6 20-BIT ADDRESSING PIC
The 20-bit addressing family of PIC processors support the
following assembler arguments:
(*)f(,a)
(*)f,(#)d(,(#)a)
(*)f,(#)s
(*)f,(#)b(,(#)a)
(*)fs,(*)fd
(#)t,(*)f
(#)t,(#)i,(*)f
ASPIC ASSEMBLER PAGE BI-11
20-BIT ADDRESSING PIC
{#}k
label(,(#)s)
((#)s)
mm
where: f register file address
fs register file source
fd register file destination
a ram access bit
(0, -> ACCESS RAM)
(1, -> RAM BANK)
d destination select:
(0, -> w), (1 -> f)
the letters w or f may be used
to select the destination
s fast call/return mode:
(0, -> SLOW), (1, -> FAST)
b bit address of an 8-bit file register
mm TBLRD and TBLWT suffixs
('*', -> no change)
('*+', -> post-increment)
('*-', -> post-decrement)
('+*', -> pre-increment)
k literal constant
label label name
Items enclosed in () are optional.
The terms f, fs, fd, a, b, d, s, k, and label may all be
expressions.
Note that not all addressing modes are valid with every in-
struction, refer to the processor specific technical data for
valid modes.
PIC18CXXX CPU Type
PIC18C242, PIC18C252
PIC18C442, PIC18C452
PIC18C658, PIC18C858
ASPIC ASSEMBLER PAGE BI-12
PIC OPCODES
BI.7 PIC OPCODES
The following table contains all the mnemonics recognized
by the ASPIC assembler. The processors supporting each mnemonic
are indicated by the code 'PIC:12:14:16:20' after each instruc-
tion type. The designation [] refers to a required addressing
mode argument.
addfsr [] PIC:--:--:--:20
addulnk [] PIC:--:--:--:20
addwf [] PIC:12:14:16:20
addwfc [] PIC:--:--:16:20
andwf [] PIC:12:14:16:20
comf [] PIC:12:14:16:20
decf [] PIC:12:14:16:20
decfsz [] PIC:12:14:16:20
dcfsnz [] PIC:--:--:16:20
incf [] PIC:12:14:16:20
incfsz [] PIC:12:14:16:20
infsnz [] PIC:--:--:16:20
iorwf [] PIC:12:14:16:20
movf [] PIC:12:14:--:20
negw [] PIC:--:--:16:--
rlf [] PIC:12:14:--:--
rlcf [] PIC:--:--:16:20
rlncf [] PIC:--:--:16:20
rrf [] PIC:12:14:--:--
rrcf [] PIC:--:--:16:20
rrncf [] PIC:--:--:16:20
subfsr [] PIC:--:--:--:20
subfwb [] PIC:--:--:--:20
subulnk [] PIC:--:--:--:20
subwf [] PIC:12:14:16:20
subwfb [] PIC:--:--:16:20
swapf [] PIC:12:14:16:20
xorwf [] PIC:12:14:16:20
movfp [] PIC:--:--:16:--
movpf [] PIC:--:--:16:--
movlb [] PIC:--:--:16:20
movlr [] PIC:--:--:16:--
movff [] PIC:--:--:--:20
movsf [] PIC:--:--:--:20
movss [] PIC:--:--:--:20
ASPIC ASSEMBLER PAGE BI-13
PIC OPCODES
lfsr [] PIC:--:--:--:20
clrf [] PIC:12:14:16:20
cpfseq [] PIC:--:--:16:20
cpfsgt [] PIC:--:--:16:20
cpfslt [] PIC:--:--:16:20
movwf [] PIC:12:14:16:20
mulwf [] PIC:--:--:16:20
negf [] PIC:--:--:--:20
setf [] PIC:--:--:16:20
tstfsz [] PIC:--:--:16:20
bcf [] PIC:12:14:16:20
bsf [] PIC:12:14:16:20
btfsc [] PIC:12:14:16:20
btfss [] PIC:12:14:16:20
btg [] PIC:--:--:16:20
addlw [] PIC:--:14:16:20
andlw [] PIC:12:14:16:20
iorlw [] PIC:12:14:16:20
movlw [] PIC:12:14:16:20
mullw [] PIC:--:--:16:20
retlw [] PIC:12:14:16:20
sublw [] PIC:--:14:16:20
xorlw [] PIC:12:14:16:20
call [] PIC:12:14:16:20
callw PIC:--:--:--:20
goto [] PIC:12:14:16:20
lcall [] PIC:--:--:16:--
bc [] PIC:--:--:--:20
bn [] PIC:--:--:--:20
bnc [] PIC:--:--:--:20
bnn [] PIC:--:--:--:20
bnov [] PIC:--:--:--:20
bnc [] PIC:--:--:--:20
bov [] PIC:--:--:--:20
bz [] PIC:--:--:--:20
bra [] PIC:--:--:--:20
rcall [] PIC:--:--:--:20
tablrd [] PIC:--:--:16:--
tablwt [] PIC:--:--:16:--
tlrd [] PIC:--:--:16:--
tlwt [] PIC:--:--:16:--
tblrd [] PIC:--:--:--:20
ASPIC ASSEMBLER PAGE BI-14
PIC OPCODES
tblwt [] PIC:--:--:--:20
clrw [] PIC:12:14:--:--
clrwdt PIC:12:14:16:20
daw PIC:--:--:16:20
nop PIC:12:14:16:20
option PIC:12:14:--:--
pop PIC:--:--:--:20
push PIC:--:--:--:20
pushl [] PIC:--:--:--:20
retfie [] PIC:--:14:16:20
return [] PIC:--:14:16:20
sleep PIC:12:14:16:20
tris [] PIC:12:14:--:--
APPENDIX BJ
ASRAB ASSEMBLER
BJ.1 ACKNOWLEDGMENT
Thanks to Ulrich Raich and Razaq Ijoduola for their contri-
bution of the ASRAB cross assembler.
Ulrich Raich and Razaq Ijoduola
PS Division
CERN
CH-1211 Geneva-23
Ulrich Raich
Ulrich dot Raich at cern dot ch
BJ.2 PROCESSOR SPECIFIC DIRECTIVES
The ASRAB assembler is a port of the ASZ80 assembler. This
assembler can process Z80, HD64180 (Z180), and Rabbit 2000/3000
(default) code. The following processor specific assembler
directives specify which processor to target when processing the
input assembler files.
ASRAB ASSEMBLER PAGE BJ-2
PROCESSOR SPECIFIC DIRECTIVES
BJ.2.1 .r2k Directive
Format:
.r2k
The .r2k directive enables processing of the Rabbit 2000/3000
specific mnemonics. Mnemonics not associated with the Rabbit
2000/3000 processor will be flagged with an