/* i40pst.c */

/*
 *  Copyright (C) 2021-2026  Alan R. Baldwin
 *
 *  This program is free software: you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation, either version 3 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Alan R. Baldwin
 * 721 Berkeley St.
 * Kent, Ohio  44240
 */

#include "asxxxx.h"
#include "i40.h"

/*
 * Coding Banks
 */
struct	bank	bank[2] = {
    /*	The '_CODE' area/bank has a NULL default file suffix.	*/
    {	NULL,		"_CSEG",	NULL,		0,	0,	0,	0,	0	},
    {	&bank[0],	"_DSEG",	"_DS",		1,	0,	0,	0,	B_FSFX	}
};

/*
 * Coding Areas
 */
struct	area	area[2] = {
    {	NULL,		&bank[0],	"_CODE",	0,	0,	0,	A_1BYTE|A_BNK|A_CSEG	},
    {	&area[0],	&bank[1],	"_DATA",	1,	0,	0,	A_1BYTE|A_BNK|A_DSEG	}
};

/*
 * Basic Relocation Mode Definition
 *
 *	#define		R_NORM	0000		No Bit Positioning
 */
char	mode0[32] = {	/* R_NORM */
	'\200',	'\201',	'\202',	'\203',	'\204',	'\205',	'\206',	'\207',
	'\210',	'\211',	'\212',	'\213',	'\214',	'\215',	'\216',	'\217',
	'\220',	'\221',	'\222',	'\223',	'\224',	'\225',	'\226',	'\227',
	'\230',	'\231',	'\232',	'\233',	'\234',	'\235',	'\236',	'\237'
};

/*
 * Additional Relocation Mode Definitions
 *
 *	#define		R_3BIT	0100		------------xxx-
 */
char	mode1[32] = {	/* R_3BIT */
	'\201',	'\202',	'\203',	'\003',	'\004',	'\005',	'\006',	'\007',
	'\010',	'\011',	'\012',	'\013',	'\014',	'\015',	'\016',	'\017',
	'\020',	'\021',	'\022',	'\023',	'\024',	'\025',	'\026',	'\027',
	'\030',	'\031',	'\032',	'\033',	'\034',	'\035',	'\036',	'\037'
};

/*
 *	#define		R_4BIT	0200		------------xxxx
 */
char	mode2[32] = {	/* R_4BIT */
	'\200',	'\201',	'\202',	'\203',	'\004',	'\005',	'\006',	'\007',
	'\010',	'\011',	'\012',	'\013',	'\014',	'\015',	'\016',	'\017',
	'\020',	'\021',	'\022',	'\023',	'\024',	'\025',	'\026',	'\027',
	'\030',	'\031',	'\032',	'\033',	'\034',	'\035',	'\036',	'\037'
};

/*
 *	#define		R_12BIT	0300		----xxxxxxxxxxxx
 */
char	mode3[32] = {	/* R_12BIT */
	'\200',	'\201',	'\202',	'\203',	'\204',	'\205',	'\206',	'\207',
	'\210',	'\211',	'\212',	'\213',	'\014',	'\015',	'\016',	'\017',
	'\020',	'\021',	'\022',	'\023',	'\024',	'\025',	'\026',	'\027',
	'\030',	'\031',	'\032',	'\033',	'\034',	'\035',	'\036',	'\037'
};


/*
 *     *m_def is a pointer to the bit relocation definition.
 *	m_flag indicates that bit position swapping is required.
 *	m_dbits contains the active bit positions for the output.
 *	m_sbits contains the active bit positions for the input.
 *
 *	struct	mode
 *	{
 *		char *	m_def;		Bit Relocation Definition
 *		a_uint	m_flag;		Bit Swapping Flag
 *		a_uint	m_dbits;	Destination Bit Mask
 *		a_uint	m_sbits;	Source Bit Mask
 *	};
 */
struct	mode	mode[4] = {
    {	&mode0[0],	0,	0x0000FFFF,	0x0000FFFF	},
    {	&mode1[0],	1,	0x0000000E,	0x00000007	},
    {	&mode2[0],	0,	0x0000000F,	0x0000000F	},
    {	&mode3[0],	0,	0x00000FFF,	0x00000FFF	}
};

/*
 * Array of Pointers to mode Structures
 */
struct	mode	*modep[16] = {
	&mode[0],	&mode[1],	&mode[2],	&mode[3],
	NULL,		NULL,		NULL,		NULL,
	NULL,		NULL,		NULL,		NULL,
	NULL,		NULL,		NULL,		NULL
};

/*
 * Mnemonic Structure
 */
struct	mne	mne[] = {

	/* assembler */

    {	NULL,	".enabl",	S_OPTN,		0,	O_ENBL	},
    {	NULL,	".dsabl",	S_OPTN,		0,	O_DSBL	},
    {	NULL,	".page",	S_PAGE,		0,	0	},
    {	NULL,	".title",	S_HEADER,	0,	O_TITLE	},
    {	NULL,	".sbttl",	S_HEADER,	0,	O_SBTTL	},
    {	NULL,	".module",	S_MODUL,	0,	0	},
    {	NULL,	".include",	S_INCL,		0,	I_CODE	},
    {	NULL,	".incbin",	S_INCL,		0,	I_BNRY	},
    {	NULL,	".area",	S_AREA,		0,	0	},
    {	NULL,	".psharea",	S_AREA,		0,	O_PSH	},
    {	NULL,	".poparea",	S_AREA,		0,	O_POP	},
    {	NULL,	".bank",	S_BANK,		0,	0	},
    {	NULL,	".org",		S_ORG,		0,	0	},
    {	NULL,	".radix",	S_RADIX,	0,	0	},
    {	NULL,	".globl",	S_GLOBL,	0,	0	},
    {	NULL,	".local",	S_LOCAL,	0,	0	},
    {	NULL,	".if",		S_CONDITIONAL,	0,	O_IF	},
    {	NULL,	".iff",		S_CONDITIONAL,	0,	O_IFF	},
    {	NULL,	".ift",		S_CONDITIONAL,	0,	O_IFT	},
    {	NULL,	".iftf",	S_CONDITIONAL,	0,	O_IFTF	},
    {	NULL,	".ifdef",	S_CONDITIONAL,	0,	O_IFDEF	},
    {	NULL,	".ifndef",	S_CONDITIONAL,	0,	O_IFNDEF},
    {	NULL,	".ifgt",	S_CONDITIONAL,	0,	O_IFGT	},
    {	NULL,	".iflt",	S_CONDITIONAL,	0,	O_IFLT	},
    {	NULL,	".ifge",	S_CONDITIONAL,	0,	O_IFGE	},
    {	NULL,	".ifle",	S_CONDITIONAL,	0,	O_IFLE	},
    {	NULL,	".ifeq",	S_CONDITIONAL,	0,	O_IFEQ	},
    {	NULL,	".ifne",	S_CONDITIONAL,	0,	O_IFNE	},
    {	NULL,	".ifb",		S_CONDITIONAL,	0,	O_IFB	},
    {	NULL,	".ifnb",	S_CONDITIONAL,	0,	O_IFNB	},
    {	NULL,	".ifidn",	S_CONDITIONAL,	0,	O_IFIDN	},
    {	NULL,	".ifdif",	S_CONDITIONAL,	0,	O_IFDIF	},
    {	NULL,	".iif",		S_CONDITIONAL,	0,	O_IIF	},
    {	NULL,	".iiff",	S_CONDITIONAL,	0,	O_IIFF	},
    {	NULL,	".iift",	S_CONDITIONAL,	0,	O_IIFT	},
    {	NULL,	".iiftf",	S_CONDITIONAL,	0,	O_IIFTF	},
    {	NULL,	".iifdef",	S_CONDITIONAL,	0,	O_IIFDEF},
    {	NULL,	".iifndef",	S_CONDITIONAL,	0,	O_IIFNDEF},
    {	NULL,	".iifgt",	S_CONDITIONAL,	0,	O_IIFGT	},
    {	NULL,	".iiflt",	S_CONDITIONAL,	0,	O_IIFLT	},
    {	NULL,	".iifge",	S_CONDITIONAL,	0,	O_IIFGE	},
    {	NULL,	".iifle",	S_CONDITIONAL,	0,	O_IIFLE	},
    {	NULL,	".iifeq",	S_CONDITIONAL,	0,	O_IIFEQ	},
    {	NULL,	".iifne",	S_CONDITIONAL,	0,	O_IIFNE	},
    {	NULL,	".iifb",	S_CONDITIONAL,	0,	O_IIFB	},
    {	NULL,	".iifnb",	S_CONDITIONAL,	0,	O_IIFNB	},
    {	NULL,	".iifidn",	S_CONDITIONAL,	0,	O_IIFIDN},
    {	NULL,	".iifdif",	S_CONDITIONAL,	0,	O_IIFDIF},
    {	NULL,	".else",	S_CONDITIONAL,	0,	O_ELSE	},
    {	NULL,	".endif",	S_CONDITIONAL,	0,	O_ENDIF	},
    {	NULL,	".list",	S_LISTING,	0,	O_LIST	},
    {	NULL,	".nlist",	S_LISTING,	0,	O_NLIST	},
    {	NULL,	".equ",		S_EQU,		0,	O_EQU	},
    {	NULL,	".gblequ",	S_EQU,		0,	O_GBLEQU},
    {	NULL,	".lclequ",	S_EQU,		0,	O_LCLEQU},
    {	NULL,	".byte",	S_DATA,		0,	O_1BYTE	},
    {	NULL,	".db",		S_DATA,		0,	O_1BYTE	},
    {	NULL,	".fcb",		S_DATA,		0,	O_1BYTE	},
    {	NULL,	".word",	S_DATA,		0,	O_2BYTE	},
    {	NULL,	".dw",		S_DATA,		0,	O_2BYTE	},
    {	NULL,	".fdb",		S_DATA,		0,	O_2BYTE	},
/*    {	NULL,	".3byte",	S_DATA,		0,	O_3BYTE	},	*/
/*    {	NULL,	".triple",	S_DATA,		0,	O_3BYTE	},	*/
/*    {	NULL,	".dl",		S_DATA,		0,	O_4BYTE	},	*/
/*    {	NULL,	".4byte",	S_DATA,		0,	O_4BYTE	},	*/
/*    {	NULL,	".quad",	S_DATA,		0,	O_4BYTE	},	*/
/*    {	NULL,	".long",	S_DATA,		0,	O_4BYTE	},	*/
    {	NULL,	".blkb",	S_BLK,		0,	O_1BYTE	},
    {	NULL,	".ds",		S_BLK,		0,	O_1BYTE	},
    {	NULL,	".rmb",		S_BLK,		0,	O_1BYTE	},
    {	NULL,	".rs",		S_BLK,		0,	O_1BYTE	},
    {	NULL,	".blkw",	S_BLK,		0,	O_2BYTE	},
/*    {	NULL,	".blk3",	S_BLK,		0,	O_3BYTE	},	*/
/*    {	NULL,	".blk4",	S_BLK,		0,	O_4BYTE	},	*/
/*    {	NULL,	".blkl",	S_BLK,		0,	O_4BYTE	},	*/
    {	NULL,	".ascii",	S_ASCIX,	0,	O_ASCII	},
    {	NULL,	".ascis",	S_ASCIX,	0,	O_ASCIS	},
    {	NULL,	".asciz",	S_ASCIX,	0,	O_ASCIZ	},
    {	NULL,	".str",		S_ASCIX,	0,	O_ASCII	},
    {	NULL,	".strs",	S_ASCIX,	0,	O_ASCIS	},
    {	NULL,	".strz",	S_ASCIX,	0,	O_ASCIZ	},
    {	NULL,	".fcc",		S_ASCIX,	0,	O_ASCII	},
    {	NULL,	".define",	S_DEFINE,	0,	O_DEF	},
    {	NULL,	".undefine",	S_DEFINE,	0,	O_UNDEF	},
    {	NULL,	".even",	S_BOUNDARY,	0,	O_EVEN	},
    {	NULL,	".odd",		S_BOUNDARY,	0,	O_ODD	},
    {	NULL,	".bndry",	S_BOUNDARY,	0,	O_BNDRY	},
    {	NULL,	".msg"	,	S_MSG,		0,	0	},
    {	NULL,	".assume",	S_ERROR,	0,	O_ASSUME},
    {	NULL,	".error",	S_ERROR,	0,	O_ERROR	},
/*    {	NULL,	".msb",		S_MSB,		0,	0	},	*/
/*    {	NULL,	".lohi",	S_MSB,		0,	O_LOHI	},	*/
/*    {	NULL,	".hilo",	S_MSB,		0,	O_HILO	},	*/
/*    {	NULL,	".8bit",	S_BITS,		0,	O_1BYTE	},	*/
/*    {	NULL,	".16bit",	S_BITS,		0,	O_2BYTE	},	*/
/*    {	NULL,	".24bit",	S_BITS,		0,	O_3BYTE	},	*/
/*    {	NULL,	".32bit",	S_BITS,		0,	O_4BYTE	},	*/
    {	NULL,	".trace",	S_TRACE,	0,	O_TRC	},
    {	NULL,	".ntrace",	S_TRACE,	0,	O_NTRC	},
/*    {	NULL,	"_______",	S_CONST,	0,	VALUE	},	*/
    {	NULL,	".end",		S_END,		0,	0	},

	/* Macro Processor */

    {	NULL,	".macro",	S_MACRO,	0,	O_MACRO	},
    {	NULL,	".endm",	S_MACRO,	0,	O_ENDM	},
    {	NULL,	".mexit",	S_MACRO,	0,	O_MEXIT	},

    {	NULL,	".narg",	S_MACRO,	0,	O_NARG	},
    {	NULL,	".nchr",	S_MACRO,	0,	O_NCHR	},
    {	NULL,	".ntyp",	S_MACRO,	0,	O_NTYP	},

    {	NULL,	".irp",		S_MACRO,	0,	O_IRP	},
    {	NULL,	".irpc",	S_MACRO,	0,	O_IRPC	},
    {	NULL,	".rept",	S_MACRO,	0,	O_REPT	},

    {	NULL,	".nval",	S_MACRO,	0,	O_NVAL	},

    {	NULL,	".mdelete",	S_MACRO,	0,	O_MDEL	},

	/* 4004 */

    {	NULL,	".4004",	S_CPU,		0,	S_4004	},

	/* Defined Constants */

    {	NULL,	"nc",		S_CONST,	0,	0x40	},	/* no condition */
    {	NULL,	"tz",		S_CONST,	0,	0x11	},	/* test equals zero */
    {	NULL,	"t0",		S_CONST,	0,	0x11	},
    {	NULL,	"cn",		S_CONST,	0,	0x12	},	/* carry equals one */
    {	NULL,	"c1",		S_CONST,	0,	0x12	},
    {	NULL,	"az",		S_CONST,	0,	0x14	},	/* accumulator equals zero */
    {	NULL,	"a0",		S_CONST,	0,	0x14	},
    {	NULL,	"tn",		S_CONST,	0,	0x29	},	/* test equals one */
    {	NULL,	"t1",		S_CONST,	0,	0x29	},
    {	NULL,	"cz",		S_CONST,	0,	0x2A	},	/* carry equals zero */
    {	NULL,	"c0",		S_CONST,	0,	0x2A	},
    {	NULL,	"an",		S_CONST,	0,	0x2C	},	/* accumulator non zero */
    {	NULL,	"nza",		S_CONST,	0,	0x2C	},

	/* Basic Instruction Set */

    {	NULL,	"nop",		S_I04,		0,	0x00	},

    {	NULL,	"jcn",		S_JCN,		0,	0x10	},
    {	NULL,	"fim",		S_FIM,		0,	0x20	},
    {	NULL,	"src",		S_SRC,		0,	0x21	},
    {	NULL,	"fin",		S_FIN,		0,	0x30	},
    {	NULL,	"jin",		S_JIN,		0,	0x31	},
    {	NULL,	"jun",		S_JUN,		0,	0x40	},
    {	NULL,	"jms",		S_JMS,		0,	0x50	},
    {	NULL,	"inc",		S_INC,		0,	0x60	},
    {	NULL,	"isz",		S_ISZ,		0,	0x70	},
    {	NULL,	"add",		S_ADD,		0,	0x80	},
    {	NULL,	"sub",		S_SUB,		0,	0x90	},
    {	NULL,	"ld",		S_LD,		0,	0xA0	},
    {	NULL,	"xch",		S_XCH,		0,	0xB0	},
    {	NULL,	"bbl",		S_BBL,		0,	0xC0	},
    {	NULL,	"ldm",		S_LDM,		0,	0xD0	},

    	/* Input/Output And RAM Instructions */

    {	NULL,	"wrm",		S_I04,		0,	0xE0	},
    {	NULL,	"wmp",		S_I04,		0,	0xE1	},
    {	NULL,	"wrr",		S_I04,		0,	0xE2	},
    {	NULL,	"wpm",		S_I04,		0,	0xE3	},
    {	NULL,	"wr0",		S_I04,		0,	0xE4	},
    {	NULL,	"wr1",		S_I04,		0,	0xE5	},
    {	NULL,	"wr2",		S_I04,		0,	0xE6	},
    {	NULL,	"wr3",		S_I04,		0,	0xE7	},
    {	NULL,	"sbm",		S_I04,		0,	0xE8	},
    {	NULL,	"rdm",		S_I04,		0,	0xE9	},
    {	NULL,	"rdr",		S_I04,		0,	0xEA	},
    {	NULL,	"adm",		S_I04,		0,	0xEB	},
    {	NULL,	"rd0",		S_I04,		0,	0xEC	},
    {	NULL,	"rd1",		S_I04,		0,	0xED	},
    {	NULL,	"rd2",		S_I04,		0,	0xEE	},
    {	NULL,	"rd3",		S_I04,		0,	0xEF	},

    	/* Accumulator Group Instructions */

    {	NULL,	"clb",		S_I04,		0,	0xF0	},
    {	NULL,	"clc",		S_I04,		0,	0xF1	},
    {	NULL,	"iac",		S_I04,		0,	0xF2	},
    {	NULL,	"cmc",		S_I04,		0,	0xF3	},
    {	NULL,	"cma",		S_I04,		0,	0xF4	},
    {	NULL,	"ral",		S_I04,		0,	0xF5	},
    {	NULL,	"rar",		S_I04,		0,	0xF6	},
    {	NULL,	"tcc",		S_I04,		0,	0xF7	},
    {	NULL,	"dac",		S_I04,		0,	0xF8	},
    {	NULL,	"tcs",		S_I04,		0,	0xF9	},
    {	NULL,	"stc",		S_I04,		0,	0xFA	},
    {	NULL,	"daa",		S_I04,		0,	0xFB	},
    {	NULL,	"kbp",		S_I04,		0,	0xFC	},
    {	NULL,	"dcl",		S_I04,		0,	0xFD	},

	/* Extended Jump On Condition Mnemonics */

    {	NULL,	"jtz",		S_JCC,		0,	0x11	},
    {	NULL,	"jto",		S_JCC,		0,	0x11	},
    {	NULL,	"jtn",		S_JCC,		0,	0x19	},
    {	NULL,	"jcz",		S_JCC,		0,	0x12	},
    {	NULL,	"joc",		S_JCC,		0,	0x12	},
    {	NULL,	"jco",		S_JCC,		0,	0x12	},
    {	NULL,	"jnc",		S_JCC,		0,	0x1A	},
    {	NULL,	"jaz",		S_JCC,		0,	0x14	},
    {	NULL,	"jnz",		S_JCC,		0,	0x1C	},
    {	NULL,	"jan",		S_JCC,		0,	0x1C	},

	/* 4040 */

    {	NULL,	".4040",	S_CPU,		0,	S_4040	},

    {	NULL,	"hlt",		S_I40,		0,	0x01	},
    {	NULL,	"bbs",		S_I40,		0,	0x02	},
    {	NULL,	"lcr",		S_I40,		0,	0x03	},
    {	NULL,	"or4",		S_I40,		0,	0x04	},
    {	NULL,	"or5",		S_I40,		0,	0x05	},
    {	NULL,	"an6",		S_I40,		0,	0x06	},
    {	NULL,	"an7",		S_I40,		0,	0x07	},
    {	NULL,	"db0",		S_I40,		0,	0x08	},
    {	NULL,	"db1",		S_I40,		0,	0x09	},
    {	NULL,	"sb0",		S_I40,		0,	0x0A	},
    {	NULL,	"sb1",		S_I40,		0,	0x0B	},
    {	NULL,	"ein",		S_I40,		0,	0x0C	},
    {	NULL,	"din",		S_I40,		0,	0x0D	},
    {	NULL,	"rpm",		S_I40,		S_EOL,	0x0E	}
};

